lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameInfo.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/FormattedStream.h"
  20 #include "llvm/Target/TargetOptions.h"
  21 #include "llvm/Target/TargetRegistry.h"
  22 using namespace llvm;
  23
  24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  25   Triple TheTriple(TT);
  26   switch (TheTriple.getOS()) {
  27   case Triple::Darwin:
  28     return new ARMMCAsmInfoDarwin();
  29   default:
  30     return new ARMELFMCAsmInfo();
  31   }
  32 }
  33
  34
  35 extern "C" void LLVMInitializeARMTarget() {
  36   // Register the target.
  37   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  38   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  39
  40   // Register the target asm info.
  41   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  42   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  43 }
  44
  45 /// TargetMachine ctor - Create an ARM architecture model.
  46 ///
  47 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  48                                            const std::string &TT,
  49                                            const std::string &FS,
  50                                            bool isThumb)
  51   : LLVMTargetMachine(T, TT),
  52     Subtarget(TT, FS, isThumb),
  53     FrameInfo(Subtarget),
  54     JITInfo(),
  55     InstrItins(Subtarget.getInstrItineraryData()) {
  56   DefRelocModel = getRelocationModel();
  57 }
  58
  59 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  60                                    const std::string &FS)
  61   : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
  62     DataLayout(Subtarget.isAPCS_ABI() ?
  63                std::string("e-p:32:32-f64:32:32-i64:32:32-"
  64                            "v128:32:128-v64:32:64-n32") :
  65                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  66                            "v128:64:128-v64:64:64-n32")),
  67     TLInfo(*this),
  68     TSInfo(*this) {
  69 }
  70
  71 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
  72                                        const std::string &FS)
  73   : ARMBaseTargetMachine(T, TT, FS, true),
  74     InstrInfo(Subtarget.hasThumb2()
  75               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
  76               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
  77     DataLayout(Subtarget.isAPCS_ABI() ?
  78                std::string("e-p:32:32-f64:32:32-i64:32:32-"
  79                            "i16:16:32-i8:8:32-i1:8:32-"
  80                            "v128:32:128-v64:32:64-a:0:32-n32") :
  81                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  82                            "i16:16:32-i8:8:32-i1:8:32-"
  83                            "v128:64:128-v64:64:64-a:0:32-n32")),
  84     TLInfo(*this),
  85     TSInfo(*this) {
  86 }
  87
  88
  89
  90 // Pass Pipeline Configuration
  91 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
  92                                            CodeGenOpt::Level OptLevel) {
  93   PM.add(createARMISelDag(*this, OptLevel));
  94   return false;
  95 }
  96
  97 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
  98                                           CodeGenOpt::Level OptLevel) {
  99   if (Subtarget.hasNEON())
 100     PM.add(createNEONPreAllocPass());
 101
 102   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 103   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 104     PM.add(createARMLoadStoreOptimizationPass(true));
 105
 106   return true;
 107 }
 108
 109 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 110                                         CodeGenOpt::Level OptLevel) {
 111   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 112   if (OptLevel != CodeGenOpt::None) {
 113     if (!Subtarget.isThumb1Only())
 114       PM.add(createARMLoadStoreOptimizationPass());
 115     if (Subtarget.hasNEON())
 116       PM.add(createNEONMoveFixPass());
 117   }
 118
 119   // Expand some pseudo instructions into multiple instructions to allow
 120   // proper scheduling.
 121   PM.add(createARMExpandPseudoPass());
 122
 123   if (OptLevel != CodeGenOpt::None) {
 124     if (!Subtarget.isThumb1Only())
 125       PM.add(createIfConverterPass());
 126   }
 127   if (Subtarget.isThumb2())
 128     PM.add(createThumb2ITBlockPass());
 129
 130   return true;
 131 }
 132
 133 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 134                                           CodeGenOpt::Level OptLevel) {
 135   if (Subtarget.isThumb2())
 136     PM.add(createThumb2SizeReductionPass());
 137
 138   PM.add(createARMConstantIslandPass());
 139   return true;
 140 }
 141
 142 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 143                                           CodeGenOpt::Level OptLevel,
 144                                           JITCodeEmitter &JCE) {
 145   // FIXME: Move this to TargetJITInfo!
 146   if (DefRelocModel == Reloc::Default)
 147     setRelocationModel(Reloc::Static);
 148
 149   // Machine code emitter pass for ARM.
 150   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 151   return false;
 152 }