1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMFrameLowering.h"
15 #include "ARMTargetMachine.h"
16 #include "ARMTargetObjectFile.h"
17 #include "ARMTargetTransformInfo.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/FormattedStream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Transforms/Scalar.h"
30 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
31 cl::desc("Inhibit optimization of S->D register accesses on A15"),
35 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
36 cl::desc("Run SimplifyCFG after expanding atomic operations"
37 " to make use of cmpxchg flow-based information"),
41 EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
42 cl::desc("Enable ARM load/store optimization pass"),
45 // FIXME: Unify control over GlobalMerge.
46 static cl::opt<cl::boolOrDefault>
47 EnableGlobalMerge("arm-global-merge", cl::Hidden,
48 cl::desc("Enable the global merge pass"));
50 extern "C" void LLVMInitializeARMTarget() {
51 // Register the target.
52 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
53 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
54 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
55 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
58 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
59 if (TT.isOSBinFormatMachO())
60 return make_unique<TargetLoweringObjectFileMachO>();
62 return make_unique<TargetLoweringObjectFileCOFF>();
63 return make_unique<ARMElfTargetObjectFile>();
66 static ARMBaseTargetMachine::ARMABI
67 computeTargetABI(const Triple &TT, StringRef CPU,
68 const TargetOptions &Options) {
69 if (Options.MCOptions.getABIName().startswith("aapcs"))
70 return ARMBaseTargetMachine::ARM_ABI_AAPCS;
71 else if (Options.MCOptions.getABIName().startswith("apcs"))
72 return ARMBaseTargetMachine::ARM_ABI_APCS;
74 assert(Options.MCOptions.getABIName().empty() &&
75 "Unknown target-abi option!");
77 ARMBaseTargetMachine::ARMABI TargetABI =
78 ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
80 // FIXME: This is duplicated code from the front end and should be unified.
81 if (TT.isOSBinFormatMachO()) {
82 if (TT.getEnvironment() == llvm::Triple::EABI ||
83 (TT.getOS() == llvm::Triple::UnknownOS &&
84 TT.getObjectFormat() == llvm::Triple::MachO) ||
85 CPU.startswith("cortex-m")) {
86 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
88 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
90 } else if (TT.isOSWindows()) {
91 // FIXME: this is invalid for WindowsCE
92 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
94 // Select the default based on the platform.
95 switch (TT.getEnvironment()) {
96 case llvm::Triple::Android:
97 case llvm::Triple::GNUEABI:
98 case llvm::Triple::GNUEABIHF:
99 case llvm::Triple::EABIHF:
100 case llvm::Triple::EABI:
101 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
103 case llvm::Triple::GNU:
104 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
107 if (TT.getOS() == llvm::Triple::NetBSD)
108 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
110 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
118 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
119 const TargetOptions &Options,
121 auto ABI = computeTargetABI(TT, CPU, Options);
122 std::string Ret = "";
131 Ret += DataLayout::getManglingComponent(TT);
133 // Pointers are 32 bits and aligned to 32 bits.
136 // ABIs other than APCS have 64 bit integers with natural alignment.
137 if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
140 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
141 // bits, others to 64 bits. We always try to align to 64 bits.
142 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
145 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
146 // to 64. We always ty to give them natural alignment.
147 if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
148 Ret += "-v64:32:64-v128:32:128";
150 Ret += "-v128:64:128";
152 // Try to align aggregates to 32 bits (the default is 64 bits, which has no
153 // particular hardware support on 32-bit ARM).
156 // Integer registers are 32 bits.
159 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
160 // aligned everywhere else.
163 else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
171 /// TargetMachine ctor - Create an ARM architecture model.
173 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
174 StringRef CPU, StringRef FS,
175 const TargetOptions &Options,
176 Reloc::Model RM, CodeModel::Model CM,
177 CodeGenOpt::Level OL, bool isLittle)
178 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
179 CPU, FS, Options, RM, CM, OL),
180 TargetABI(computeTargetABI(TT, CPU, Options)),
181 TLOF(createTLOF(getTargetTriple())),
182 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
184 // Default to triple-appropriate float ABI
185 if (Options.FloatABIType == FloatABI::Default)
186 this->Options.FloatABIType =
187 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
190 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
193 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
194 Attribute CPUAttr = F.getFnAttribute("target-cpu");
195 Attribute FSAttr = F.getFnAttribute("target-features");
197 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
198 ? CPUAttr.getValueAsString().str()
200 std::string FS = !FSAttr.hasAttribute(Attribute::None)
201 ? FSAttr.getValueAsString().str()
204 // FIXME: This is related to the code below to reset the target options,
205 // we need to know whether or not the soft float flag is set on the
206 // function before we can generate a subtarget. We also need to use
207 // it as a key for the subtarget since that can be the only difference
208 // between two functions.
210 F.hasFnAttribute("use-soft-float") &&
211 F.getFnAttribute("use-soft-float").getValueAsString() == "true";
212 // If the soft float attribute is set on the function turn on the soft float
213 // subtarget feature.
215 FS += FS.empty() ? "+soft-float" : ",+soft-float";
217 auto &I = SubtargetMap[CPU + FS];
219 // This needs to be done before we create a new subtarget since any
220 // creation will depend on the TM and the code generation flags on the
221 // function that reside in TargetOptions.
222 resetTargetOptions(F);
223 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
228 TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
229 return TargetIRAnalysis(
230 [this](Function &F) { return TargetTransformInfo(ARMTTIImpl(this, F)); });
234 void ARMTargetMachine::anchor() { }
236 ARMTargetMachine::ARMTargetMachine(const Target &T, const Triple &TT,
237 StringRef CPU, StringRef FS,
238 const TargetOptions &Options,
239 Reloc::Model RM, CodeModel::Model CM,
240 CodeGenOpt::Level OL, bool isLittle)
241 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
243 if (!Subtarget.hasARMOps())
244 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
245 "support ARM mode execution!");
248 void ARMLETargetMachine::anchor() { }
250 ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
251 StringRef CPU, StringRef FS,
252 const TargetOptions &Options,
253 Reloc::Model RM, CodeModel::Model CM,
254 CodeGenOpt::Level OL)
255 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
257 void ARMBETargetMachine::anchor() { }
259 ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
260 StringRef CPU, StringRef FS,
261 const TargetOptions &Options,
262 Reloc::Model RM, CodeModel::Model CM,
263 CodeGenOpt::Level OL)
264 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
266 void ThumbTargetMachine::anchor() { }
268 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Triple &TT,
269 StringRef CPU, StringRef FS,
270 const TargetOptions &Options,
271 Reloc::Model RM, CodeModel::Model CM,
272 CodeGenOpt::Level OL, bool isLittle)
273 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
277 void ThumbLETargetMachine::anchor() { }
279 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, const Triple &TT,
280 StringRef CPU, StringRef FS,
281 const TargetOptions &Options,
282 Reloc::Model RM, CodeModel::Model CM,
283 CodeGenOpt::Level OL)
284 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
286 void ThumbBETargetMachine::anchor() { }
288 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, const Triple &TT,
289 StringRef CPU, StringRef FS,
290 const TargetOptions &Options,
291 Reloc::Model RM, CodeModel::Model CM,
292 CodeGenOpt::Level OL)
293 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
296 /// ARM Code Generator Pass Configuration Options.
297 class ARMPassConfig : public TargetPassConfig {
299 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
300 : TargetPassConfig(TM, PM) {}
302 ARMBaseTargetMachine &getARMTargetMachine() const {
303 return getTM<ARMBaseTargetMachine>();
306 void addIRPasses() override;
307 bool addPreISel() override;
308 bool addInstSelector() override;
309 void addPreRegAlloc() override;
310 void addPreSched2() override;
311 void addPreEmitPass() override;
315 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
316 return new ARMPassConfig(this, PM);
319 void ARMPassConfig::addIRPasses() {
320 if (TM->Options.ThreadModel == ThreadModel::Single)
321 addPass(createLowerAtomicPass());
323 addPass(createAtomicExpandPass(TM));
325 // Cmpxchg instructions are often used with a subsequent comparison to
326 // determine whether it succeeded. We can exploit existing control-flow in
327 // ldrex/strex loops to simplify this, but it needs tidying up.
328 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
329 addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
330 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
331 return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
334 TargetPassConfig::addIRPasses();
337 bool ARMPassConfig::addPreISel() {
338 if ((TM->getOptLevel() != CodeGenOpt::None &&
339 EnableGlobalMerge == cl::BOU_UNSET) ||
340 EnableGlobalMerge == cl::BOU_TRUE) {
341 // FIXME: This is using the thumb1 only constant value for
342 // maximal global offset for merging globals. We may want
343 // to look into using the old value for non-thumb1 code of
344 // 4095 based on the TargetMachine, but this starts to become
345 // tricky when doing code gen per function.
346 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
347 (EnableGlobalMerge == cl::BOU_UNSET);
348 addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize));
354 bool ARMPassConfig::addInstSelector() {
355 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
357 if (TM->getTargetTriple().isOSBinFormatELF() && TM->Options.EnableFastISel)
358 addPass(createARMGlobalBaseRegPass());
362 void ARMPassConfig::addPreRegAlloc() {
363 if (getOptLevel() != CodeGenOpt::None) {
364 addPass(createMLxExpansionPass());
366 if (EnableARMLoadStoreOpt)
367 addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
369 if (!DisableA15SDOptimization)
370 addPass(createA15SDOptimizerPass());
374 void ARMPassConfig::addPreSched2() {
375 if (getOptLevel() != CodeGenOpt::None) {
376 if (EnableARMLoadStoreOpt)
377 addPass(createARMLoadStoreOptimizationPass());
379 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
382 // Expand some pseudo instructions into multiple instructions to allow
383 // proper scheduling.
384 addPass(createARMExpandPseudoPass());
386 if (getOptLevel() != CodeGenOpt::None) {
387 // in v8, IfConversion depends on Thumb instruction widths
388 addPass(createThumb2SizeReductionPass([this](const Function &F) {
389 return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
392 addPass(createIfConverter([this](const Function &F) {
393 return !this->TM->getSubtarget<ARMSubtarget>(F).isThumb1Only();
396 addPass(createThumb2ITBlockPass());
399 void ARMPassConfig::addPreEmitPass() {
400 addPass(createThumb2SizeReductionPass());
402 // Constant island pass work on unbundled instructions.
403 addPass(createUnpackMachineBundles([this](const Function &F) {
404 return this->TM->getSubtarget<ARMSubtarget>(F).isThumb2();
407 // Don't optimize barriers at -O0.
408 if (getOptLevel() != CodeGenOpt::None)
409 addPass(createARMOptimizeBarriersPass());
411 addPass(createARMConstantIslandPass());