lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameInfo.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/FormattedStream.h"
  20 #include "llvm/Target/TargetOptions.h"
  21 #include "llvm/Target/TargetRegistry.h"
  22 using namespace llvm;
  23
  24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  25   Triple TheTriple(TT);
  26   switch (TheTriple.getOS()) {
  27   case Triple::Darwin:
  28     return new ARMMCAsmInfoDarwin();
  29   default:
  30     return new ARMELFMCAsmInfo();
  31   }
  32 }
  33
  34 // This is duplicated code. Refactor this.
  35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  36                                     MCContext &Ctx, TargetAsmBackend &TAB,
  37                                     raw_ostream &OS,
  38                                     MCCodeEmitter *Emitter,
  39                                     bool RelaxAll) {
  40   switch (Triple(TT).getOS()) {
  41   case Triple::Darwin:
  42     return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
  43   case Triple::MinGW32:
  44   case Triple::MinGW64:
  45   case Triple::Cygwin:
  46   case Triple::Win32:
  47     llvm_unreachable("ARM does not support Windows COFF format");
  48     return NULL;
  49   default:
  50     return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
  51   }
  52 }
  53
  54 extern "C" void LLVMInitializeARMTarget() {
  55   // Register the target.
  56   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  57   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  58
  59   // Register the target asm info.
  60   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  61   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  62
  63   // Register the MC Code Emitter
  64   TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
  65   TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
  66
  67   // Register the asm backend.
  68   TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
  69   TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
  70
  71   // Register the object streamer.
  72   TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
  73   TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
  74
  75 }
  76
  77 /// TargetMachine ctor - Create an ARM architecture model.
  78 ///
  79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  80                                            const std::string &TT,
  81                                            const std::string &FS,
  82                                            bool isThumb)
  83   : LLVMTargetMachine(T, TT),
  84     Subtarget(TT, FS, isThumb),
  85     JITInfo(),
  86     InstrItins(Subtarget.getInstrItineraryData())
  87 {
  88   DefRelocModel = getRelocationModel();
  89 }
  90
  91 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  92                                    const std::string &FS)
  93   : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
  94     DataLayout(Subtarget.isAPCS_ABI() ?
  95                std::string("e-p:32:32-f64:32:64-i64:32:64-"
  96                            "v128:32:128-v64:32:64-n32") :
  97                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  98                            "v128:64:128-v64:64:64-n32")),
  99     ELFWriterInfo(*this),
 100     TLInfo(*this),
 101     TSInfo(*this),
 102     FrameInfo(Subtarget) {
 103   if (!Subtarget.hasARMOps())
 104     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 105                        "support ARM mode execution!");
 106 }
 107
 108 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 109                                        const std::string &FS)
 110   : ARMBaseTargetMachine(T, TT, FS, true),
 111     InstrInfo(Subtarget.hasThumb2()
 112               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 113               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 114     DataLayout(Subtarget.isAPCS_ABI() ?
 115                std::string("e-p:32:32-f64:32:64-i64:32:64-"
 116                            "i16:16:32-i8:8:32-i1:8:32-"
 117                            "v128:32:128-v64:32:64-a:0:32-n32") :
 118                std::string("e-p:32:32-f64:64:64-i64:64:64-"
 119                            "i16:16:32-i8:8:32-i1:8:32-"
 120                            "v128:64:128-v64:64:64-a:0:32-n32")),
 121     ELFWriterInfo(*this),
 122     TLInfo(*this),
 123     TSInfo(*this),
 124     FrameInfo(Subtarget.hasThumb2()
 125               ? new ARMFrameInfo(Subtarget)
 126               : (ARMFrameInfo*)new Thumb1FrameInfo(Subtarget)) {
 127 }
 128
 129 // Pass Pipeline Configuration
 130 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 131                                       CodeGenOpt::Level OptLevel) {
 132   if (OptLevel != CodeGenOpt::None)
 133     PM.add(createARMGlobalMergePass(getTargetLowering()));
 134
 135   return false;
 136 }
 137
 138 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 139                                            CodeGenOpt::Level OptLevel) {
 140   PM.add(createARMISelDag(*this, OptLevel));
 141   return false;
 142 }
 143
 144 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 145                                           CodeGenOpt::Level OptLevel) {
 146   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 147   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 148     PM.add(createARMLoadStoreOptimizationPass(true));
 149
 150   return true;
 151 }
 152
 153 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 154                                         CodeGenOpt::Level OptLevel) {
 155   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 156   if (OptLevel != CodeGenOpt::None) {
 157     if (!Subtarget.isThumb1Only())
 158       PM.add(createARMLoadStoreOptimizationPass());
 159     if (Subtarget.hasNEON())
 160       PM.add(createNEONMoveFixPass());
 161   }
 162
 163   // Expand some pseudo instructions into multiple instructions to allow
 164   // proper scheduling.
 165   PM.add(createARMExpandPseudoPass());
 166
 167   if (OptLevel != CodeGenOpt::None) {
 168     if (!Subtarget.isThumb1Only())
 169       PM.add(createIfConverterPass());
 170   }
 171   if (Subtarget.isThumb2())
 172     PM.add(createThumb2ITBlockPass());
 173
 174   return true;
 175 }
 176
 177 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 178                                           CodeGenOpt::Level OptLevel) {
 179   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 180     PM.add(createThumb2SizeReductionPass());
 181
 182   PM.add(createARMConstantIslandPass());
 183   return true;
 184 }
 185
 186 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 187                                           CodeGenOpt::Level OptLevel,
 188                                           JITCodeEmitter &JCE) {
 189   // FIXME: Move this to TargetJITInfo!
 190   if (DefRelocModel == Reloc::Default)
 191     setRelocationModel(Reloc::Static);
 192
 193   // Machine code emitter pass for ARM.
 194   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 195   return false;
 196 }