1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 switch (TheTriple.getOS()) {
28 return new ARMMCAsmInfoDarwin();
30 return new ARMELFMCAsmInfo();
34 // This is duplicated code. Refactor this.
35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
36 MCContext &Ctx, TargetAsmBackend &TAB,
38 MCCodeEmitter *_Emitter,
41 switch (TheTriple.getOS()) {
43 return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
48 assert(0 && "ARM does not support Windows COFF format"); break;
50 return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
54 extern "C" void LLVMInitializeARMTarget() {
55 // Register the target.
56 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
57 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
59 // Register the target asm info.
60 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
61 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
63 // Register the MC Code Emitter
64 TargetRegistry::RegisterCodeEmitter(TheARMTarget,
65 createARMMCCodeEmitter);
66 TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
67 createARMMCCodeEmitter);
69 // Register the object streamer.
70 TargetRegistry::RegisterObjectStreamer(TheARMTarget,
72 TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
77 /// TargetMachine ctor - Create an ARM architecture model.
79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
80 const std::string &TT,
81 const std::string &FS,
83 : LLVMTargetMachine(T, TT),
84 Subtarget(TT, FS, isThumb),
87 InstrItins(Subtarget.getInstrItineraryData()),
88 DataLayout(Subtarget.getDataLayout()),
91 DefRelocModel = getRelocationModel();
94 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
95 const std::string &FS)
96 : ARMBaseTargetMachine(T, TT, FS, false),
100 if (!Subtarget.hasARMOps())
101 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
102 "support ARM mode execution!");
105 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
106 const std::string &FS)
107 : ARMBaseTargetMachine(T, TT, FS, true),
108 InstrInfo(Subtarget.hasThumb2()
109 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
110 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
115 // Pass Pipeline Configuration
116 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
117 CodeGenOpt::Level OptLevel) {
118 if (OptLevel != CodeGenOpt::None)
119 PM.add(createARMGlobalMergePass(getTargetLowering()));
124 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
125 CodeGenOpt::Level OptLevel) {
126 PM.add(createARMISelDag(*this, OptLevel));
130 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
131 CodeGenOpt::Level OptLevel) {
132 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
133 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
134 PM.add(createARMLoadStoreOptimizationPass(true));
139 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
140 CodeGenOpt::Level OptLevel) {
141 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
142 if (OptLevel != CodeGenOpt::None) {
143 if (!Subtarget.isThumb1Only())
144 PM.add(createARMLoadStoreOptimizationPass());
145 if (Subtarget.hasNEON())
146 PM.add(createNEONMoveFixPass());
149 // Expand some pseudo instructions into multiple instructions to allow
150 // proper scheduling.
151 PM.add(createARMExpandPseudoPass());
153 if (OptLevel != CodeGenOpt::None) {
154 if (!Subtarget.isThumb1Only())
155 PM.add(createIfConverterPass());
157 if (Subtarget.isThumb2())
158 PM.add(createThumb2ITBlockPass());
163 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
164 CodeGenOpt::Level OptLevel) {
165 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
166 PM.add(createThumb2SizeReductionPass());
168 PM.add(createARMConstantIslandPass());
172 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
173 CodeGenOpt::Level OptLevel,
174 JITCodeEmitter &JCE) {
175 // FIXME: Move this to TargetJITInfo!
176 if (DefRelocModel == Reloc::Default)
177 setRelocationModel(Reloc::Static);
179 // Machine code emitter pass for ARM.
180 PM.add(createARMJITCodeEmitterPass(*this, JCE));