1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
24 static const MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 switch (TheTriple.getOS()) {
28 return new ARMMCAsmInfoDarwin();
30 return new ARMELFMCAsmInfo();
35 extern "C" void LLVMInitializeARMTarget() {
36 // Register the target.
37 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
38 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
40 // Register the target asm info.
41 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
42 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
45 /// TargetMachine ctor - Create an ARM architecture model.
47 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
48 const std::string &TT,
49 const std::string &FS,
51 : LLVMTargetMachine(T, TT),
52 Subtarget(TT, FS, isThumb),
55 InstrItins(Subtarget.getInstrItineraryData()) {
56 DefRelocModel = getRelocationModel();
59 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
60 const std::string &FS)
61 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
62 DataLayout(Subtarget.isAPCS_ABI() ?
63 std::string("e-p:32:32-f64:32:32-i64:32:32-n32") :
64 std::string("e-p:32:32-f64:64:64-i64:64:64-n32")),
68 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
69 const std::string &FS)
70 : ARMBaseTargetMachine(T, TT, FS, true),
71 InstrInfo(Subtarget.hasThumb2()
72 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
73 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
74 DataLayout(Subtarget.isAPCS_ABI() ?
75 std::string("e-p:32:32-f64:32:32-i64:32:32-"
76 "i16:16:32-i8:8:32-i1:8:32-a:0:32-n32") :
77 std::string("e-p:32:32-f64:64:64-i64:64:64-"
78 "i16:16:32-i8:8:32-i1:8:32-a:0:32-n32")),
84 // Pass Pipeline Configuration
85 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
86 CodeGenOpt::Level OptLevel) {
87 PM.add(createARMISelDag(*this, OptLevel));
91 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
92 CodeGenOpt::Level OptLevel) {
93 if (Subtarget.hasNEON())
94 PM.add(createNEONPreAllocPass());
96 // Calculate and set max stack object alignment early, so we can decide
97 // whether we will need stack realignment (and thus FP).
98 PM.add(createARMMaxStackAlignmentCalculatorPass());
100 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
101 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
102 PM.add(createARMLoadStoreOptimizationPass(true));
106 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
107 CodeGenOpt::Level OptLevel) {
108 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
109 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
110 PM.add(createARMLoadStoreOptimizationPass());
112 // Expand some pseudo instructions into multiple instructions to allow
113 // proper scheduling.
114 PM.add(createARMExpandPseudoPass());
119 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
120 CodeGenOpt::Level OptLevel) {
121 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
122 if (OptLevel != CodeGenOpt::None) {
123 if (!Subtarget.isThumb1Only())
124 PM.add(createIfConverterPass());
125 if (Subtarget.hasNEON())
126 PM.add(createNEONMoveFixPass());
129 if (Subtarget.isThumb2()) {
130 PM.add(createThumb2ITBlockPass());
131 PM.add(createThumb2SizeReductionPass());
134 PM.add(createARMConstantIslandPass());
138 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
139 CodeGenOpt::Level OptLevel,
140 MachineCodeEmitter &MCE) {
141 // FIXME: Move this to TargetJITInfo!
142 if (DefRelocModel == Reloc::Default)
143 setRelocationModel(Reloc::Static);
145 // Machine code emitter pass for ARM.
146 PM.add(createARMCodeEmitterPass(*this, MCE));
150 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
151 CodeGenOpt::Level OptLevel,
152 JITCodeEmitter &JCE) {
153 // FIXME: Move this to TargetJITInfo!
154 if (DefRelocModel == Reloc::Default)
155 setRelocationModel(Reloc::Static);
157 // Machine code emitter pass for ARM.
158 PM.add(createARMJITCodeEmitterPass(*this, JCE));
162 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
163 CodeGenOpt::Level OptLevel,
164 ObjectCodeEmitter &OCE) {
165 // FIXME: Move this to TargetJITInfo!
166 if (DefRelocModel == Reloc::Default)
167 setRelocationModel(Reloc::Static);
169 // Machine code emitter pass for ARM.
170 PM.add(createARMObjectCodeEmitterPass(*this, OCE));
174 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
175 CodeGenOpt::Level OptLevel,
176 MachineCodeEmitter &MCE) {
177 // Machine code emitter pass for ARM.
178 PM.add(createARMCodeEmitterPass(*this, MCE));
182 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
183 CodeGenOpt::Level OptLevel,
184 JITCodeEmitter &JCE) {
185 // Machine code emitter pass for ARM.
186 PM.add(createARMJITCodeEmitterPass(*this, JCE));
190 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
191 CodeGenOpt::Level OptLevel,
192 ObjectCodeEmitter &OCE) {
193 // Machine code emitter pass for ARM.
194 PM.add(createARMObjectCodeEmitterPass(*this, OCE));