1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMFrameLowering.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
24 // This is duplicated code. Refactor this.
25 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
26 MCContext &Ctx, TargetAsmBackend &TAB,
28 MCCodeEmitter *Emitter,
33 if (TheTriple.isOSDarwin())
34 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
36 if (TheTriple.isOSWindows()) {
37 llvm_unreachable("ARM does not support Windows COFF format");
41 return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
44 extern "C" void LLVMInitializeARMTarget() {
45 // Register the target.
46 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
47 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
49 // Register the MC Code Emitter
50 TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
51 TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
53 // Register the asm backend.
54 TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
55 TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
57 // Register the object streamer.
58 TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
59 TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
63 /// TargetMachine ctor - Create an ARM architecture model.
65 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
66 StringRef CPU, StringRef FS,
67 Reloc::Model RM, CodeModel::Model CM)
68 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
69 Subtarget(TT, CPU, FS),
71 InstrItins(Subtarget.getInstrItineraryData()) {
72 // Default to soft float ABI
73 if (FloatABIType == FloatABI::Default)
74 FloatABIType = FloatABI::Soft;
77 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
78 StringRef CPU, StringRef FS,
79 Reloc::Model RM, CodeModel::Model CM)
80 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
81 DataLayout(Subtarget.isAPCS_ABI() ?
82 std::string("e-p:32:32-f64:32:64-i64:32:64-"
83 "v128:32:128-v64:32:64-n32") :
84 std::string("e-p:32:32-f64:64:64-i64:64:64-"
85 "v128:64:128-v64:64:64-n32")),
89 FrameLowering(Subtarget) {
90 if (!Subtarget.hasARMOps())
91 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
92 "support ARM mode execution!");
95 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
96 StringRef CPU, StringRef FS,
97 Reloc::Model RM, CodeModel::Model CM)
98 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
99 InstrInfo(Subtarget.hasThumb2()
100 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
101 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
102 DataLayout(Subtarget.isAPCS_ABI() ?
103 std::string("e-p:32:32-f64:32:64-i64:32:64-"
104 "i16:16:32-i8:8:32-i1:8:32-"
105 "v128:32:128-v64:32:64-a:0:32-n32") :
106 std::string("e-p:32:32-f64:64:64-i64:64:64-"
107 "i16:16:32-i8:8:32-i1:8:32-"
108 "v128:64:128-v64:64:64-a:0:32-n32")),
109 ELFWriterInfo(*this),
112 FrameLowering(Subtarget.hasThumb2()
113 ? new ARMFrameLowering(Subtarget)
114 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
117 // Pass Pipeline Configuration
118 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
119 CodeGenOpt::Level OptLevel) {
120 if (OptLevel != CodeGenOpt::None)
121 PM.add(createARMGlobalMergePass(getTargetLowering()));
126 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
127 CodeGenOpt::Level OptLevel) {
128 PM.add(createARMISelDag(*this, OptLevel));
132 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
133 CodeGenOpt::Level OptLevel) {
134 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
135 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
136 PM.add(createARMLoadStoreOptimizationPass(true));
137 if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
138 PM.add(createMLxExpansionPass());
143 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
144 CodeGenOpt::Level OptLevel) {
145 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
146 if (OptLevel != CodeGenOpt::None) {
147 if (!Subtarget.isThumb1Only())
148 PM.add(createARMLoadStoreOptimizationPass());
149 if (Subtarget.hasNEON())
150 PM.add(createNEONMoveFixPass());
153 // Expand some pseudo instructions into multiple instructions to allow
154 // proper scheduling.
155 PM.add(createARMExpandPseudoPass());
157 if (OptLevel != CodeGenOpt::None) {
158 if (!Subtarget.isThumb1Only())
159 PM.add(createIfConverterPass());
161 if (Subtarget.isThumb2())
162 PM.add(createThumb2ITBlockPass());
167 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
168 CodeGenOpt::Level OptLevel) {
169 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
170 PM.add(createThumb2SizeReductionPass());
172 PM.add(createARMConstantIslandPass());
176 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
177 CodeGenOpt::Level OptLevel,
178 JITCodeEmitter &JCE) {
179 // Machine code emitter pass for ARM.
180 PM.add(createARMJITCodeEmitterPass(*this, JCE));