1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
28 cl::desc("Inhibit optimization of S->D register accesses on A15"),
32 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
33 cl::desc("Run SimplifyCFG after expanding atomic operations"
34 " to make use of cmpxchg flow-based information"),
37 extern "C" void LLVMInitializeARMTarget() {
38 // Register the target.
39 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
40 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
41 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
42 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
46 /// TargetMachine ctor - Create an ARM architecture model.
48 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS,
50 const TargetOptions &Options,
51 Reloc::Model RM, CodeModel::Model CM,
54 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
55 Subtarget(TT, CPU, FS, isLittle, Options) {
57 // Default to triple-appropriate float ABI
58 if (Options.FloatABIType == FloatABI::Default)
59 this->Options.FloatABIType =
60 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
63 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
64 // Add first the target-independent BasicTTI pass, then our ARM pass. This
65 // allows the ARM pass to delegate to the target independent layer when
67 PM.add(createBasicTargetTransformInfoPass(this));
68 PM.add(createARMTargetTransformInfoPass(this));
72 void ARMTargetMachine::anchor() { }
74 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
75 StringRef CPU, StringRef FS,
76 const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
80 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
83 FrameLowering(Subtarget) {
85 if (!Subtarget.hasARMOps())
86 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
87 "support ARM mode execution!");
90 void ARMLETargetMachine::anchor() { }
93 ARMLETargetMachine(const Target &T, StringRef TT,
94 StringRef CPU, StringRef FS, const TargetOptions &Options,
95 Reloc::Model RM, CodeModel::Model CM,
97 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
99 void ARMBETargetMachine::anchor() { }
102 ARMBETargetMachine(const Target &T, StringRef TT,
103 StringRef CPU, StringRef FS, const TargetOptions &Options,
104 Reloc::Model RM, CodeModel::Model CM,
105 CodeGenOpt::Level OL)
106 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
108 void ThumbTargetMachine::anchor() { }
110 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
111 StringRef CPU, StringRef FS,
112 const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL,
116 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
117 InstrInfo(Subtarget.hasThumb2()
118 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
119 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
121 FrameLowering(Subtarget.hasThumb2()
122 ? new ARMFrameLowering(Subtarget)
123 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
127 void ThumbLETargetMachine::anchor() { }
129 ThumbLETargetMachine::
130 ThumbLETargetMachine(const Target &T, StringRef TT,
131 StringRef CPU, StringRef FS, const TargetOptions &Options,
132 Reloc::Model RM, CodeModel::Model CM,
133 CodeGenOpt::Level OL)
134 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
136 void ThumbBETargetMachine::anchor() { }
138 ThumbBETargetMachine::
139 ThumbBETargetMachine(const Target &T, StringRef TT,
140 StringRef CPU, StringRef FS, const TargetOptions &Options,
141 Reloc::Model RM, CodeModel::Model CM,
142 CodeGenOpt::Level OL)
143 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
146 /// ARM Code Generator Pass Configuration Options.
147 class ARMPassConfig : public TargetPassConfig {
149 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
150 : TargetPassConfig(TM, PM) {}
152 ARMBaseTargetMachine &getARMTargetMachine() const {
153 return getTM<ARMBaseTargetMachine>();
156 const ARMSubtarget &getARMSubtarget() const {
157 return *getARMTargetMachine().getSubtargetImpl();
160 void addIRPasses() override;
161 bool addPreISel() override;
162 bool addInstSelector() override;
163 bool addPreRegAlloc() override;
164 bool addPreSched2() override;
165 bool addPreEmitPass() override;
169 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
170 return new ARMPassConfig(this, PM);
173 void ARMPassConfig::addIRPasses() {
174 addPass(createAtomicExpandLoadLinkedPass(TM));
176 // Cmpxchg instructions are often used with a subsequent comparison to
177 // determine whether it succeeded. We can exploit existing control-flow in
178 // ldrex/strex loops to simplify this, but it needs tidying up.
179 const ARMSubtarget *Subtarget = &getARMSubtarget();
180 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
181 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
182 addPass(createCFGSimplificationPass());
184 TargetPassConfig::addIRPasses();
187 bool ARMPassConfig::addPreISel() {
188 if (TM->getOptLevel() != CodeGenOpt::None)
189 addPass(createGlobalMergePass(TM));
194 bool ARMPassConfig::addInstSelector() {
195 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
197 const ARMSubtarget *Subtarget = &getARMSubtarget();
198 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
199 TM->Options.EnableFastISel)
200 addPass(createARMGlobalBaseRegPass());
204 bool ARMPassConfig::addPreRegAlloc() {
205 if (getOptLevel() != CodeGenOpt::None)
206 addPass(createARMLoadStoreOptimizationPass(true));
207 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
208 addPass(createMLxExpansionPass());
209 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
210 // enabled when NEON is available.
211 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
212 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
213 addPass(createA15SDOptimizerPass());
218 bool ARMPassConfig::addPreSched2() {
219 if (getOptLevel() != CodeGenOpt::None) {
220 addPass(createARMLoadStoreOptimizationPass());
221 printAndVerify("After ARM load / store optimizer");
223 if (getARMSubtarget().hasNEON())
224 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
227 // Expand some pseudo instructions into multiple instructions to allow
228 // proper scheduling.
229 addPass(createARMExpandPseudoPass());
231 if (getOptLevel() != CodeGenOpt::None) {
232 if (!getARMSubtarget().isThumb1Only()) {
233 // in v8, IfConversion depends on Thumb instruction widths
234 if (getARMSubtarget().restrictIT() &&
235 !getARMSubtarget().prefers32BitThumb())
236 addPass(createThumb2SizeReductionPass());
237 addPass(&IfConverterID);
240 if (getARMSubtarget().isThumb2())
241 addPass(createThumb2ITBlockPass());
246 bool ARMPassConfig::addPreEmitPass() {
247 if (getARMSubtarget().isThumb2()) {
248 if (!getARMSubtarget().prefers32BitThumb())
249 addPass(createThumb2SizeReductionPass());
251 // Constant island pass work on unbundled instructions.
252 addPass(&UnpackMachineBundlesID);
255 addPass(createARMOptimizeBarriersPass());
256 addPass(createARMConstantIslandPass());
261 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
262 JITCodeEmitter &JCE) {
263 // Machine code emitter pass for ARM.
264 PM.add(createARMJITCodeEmitterPass(*this, JCE));