1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
28 cl::desc("Inhibit optimization of S->D register accesses on A15"),
32 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
33 cl::desc("Run SimplifyCFG after expanding atomic operations"
34 " to make use of cmpxchg flow-based information"),
37 extern "C" void LLVMInitializeARMTarget() {
38 // Register the target.
39 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
40 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
41 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
42 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
46 /// TargetMachine ctor - Create an ARM architecture model.
48 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
49 StringRef CPU, StringRef FS,
50 const TargetOptions &Options,
51 Reloc::Model RM, CodeModel::Model CM,
54 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
55 Subtarget(TT, CPU, FS, isLittle, Options),
57 InstrItins(Subtarget.getInstrItineraryData()) {
59 // Default to triple-appropriate float ABI
60 if (Options.FloatABIType == FloatABI::Default)
61 this->Options.FloatABIType =
62 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
65 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
66 // Add first the target-independent BasicTTI pass, then our ARM pass. This
67 // allows the ARM pass to delegate to the target independent layer when
69 PM.add(createBasicTargetTransformInfoPass(this));
70 PM.add(createARMTargetTransformInfoPass(this));
74 void ARMTargetMachine::anchor() { }
76 static std::string computeDataLayout(ARMSubtarget &ST) {
86 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
88 // Pointers are 32 bits and aligned to 32 bits.
91 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
94 Ret += "-i1:8:32-i8:8:32-i16:16:32";
96 // ABIs other than APCS have 64 bit integers with natural alignment.
100 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
101 // bits, others to 64 bits. We always try to align to 64 bits.
105 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
106 // to 64. We always ty to give them natural alignment.
108 Ret += "-v64:32:64-v128:32:128";
110 Ret += "-v128:64:128";
112 // On thumb and APCS, only try to align aggregates to 32 bits (the default is
114 if (ST.isThumb() || ST.isAPCS_ABI())
117 // Integer registers are 32 bits.
120 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
121 // aligned everywhere else.
122 if (ST.isTargetNaCl())
124 else if (ST.isAAPCS_ABI())
132 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
133 StringRef CPU, StringRef FS,
134 const TargetOptions &Options,
135 Reloc::Model RM, CodeModel::Model CM,
136 CodeGenOpt::Level OL,
138 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
139 InstrInfo(Subtarget),
140 DL(computeDataLayout(Subtarget)),
143 FrameLowering(Subtarget) {
145 if (!Subtarget.hasARMOps())
146 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
147 "support ARM mode execution!");
150 void ARMLETargetMachine::anchor() { }
153 ARMLETargetMachine(const Target &T, StringRef TT,
154 StringRef CPU, StringRef FS, const TargetOptions &Options,
155 Reloc::Model RM, CodeModel::Model CM,
156 CodeGenOpt::Level OL)
157 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
159 void ARMBETargetMachine::anchor() { }
162 ARMBETargetMachine(const Target &T, StringRef TT,
163 StringRef CPU, StringRef FS, const TargetOptions &Options,
164 Reloc::Model RM, CodeModel::Model CM,
165 CodeGenOpt::Level OL)
166 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
168 void ThumbTargetMachine::anchor() { }
170 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
171 StringRef CPU, StringRef FS,
172 const TargetOptions &Options,
173 Reloc::Model RM, CodeModel::Model CM,
174 CodeGenOpt::Level OL,
176 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle),
177 InstrInfo(Subtarget.hasThumb2()
178 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
179 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
180 DL(computeDataLayout(Subtarget)),
183 FrameLowering(Subtarget.hasThumb2()
184 ? new ARMFrameLowering(Subtarget)
185 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
189 void ThumbLETargetMachine::anchor() { }
191 ThumbLETargetMachine::
192 ThumbLETargetMachine(const Target &T, StringRef TT,
193 StringRef CPU, StringRef FS, const TargetOptions &Options,
194 Reloc::Model RM, CodeModel::Model CM,
195 CodeGenOpt::Level OL)
196 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
198 void ThumbBETargetMachine::anchor() { }
200 ThumbBETargetMachine::
201 ThumbBETargetMachine(const Target &T, StringRef TT,
202 StringRef CPU, StringRef FS, const TargetOptions &Options,
203 Reloc::Model RM, CodeModel::Model CM,
204 CodeGenOpt::Level OL)
205 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
208 /// ARM Code Generator Pass Configuration Options.
209 class ARMPassConfig : public TargetPassConfig {
211 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
212 : TargetPassConfig(TM, PM) {}
214 ARMBaseTargetMachine &getARMTargetMachine() const {
215 return getTM<ARMBaseTargetMachine>();
218 const ARMSubtarget &getARMSubtarget() const {
219 return *getARMTargetMachine().getSubtargetImpl();
222 void addIRPasses() override;
223 bool addPreISel() override;
224 bool addInstSelector() override;
225 bool addPreRegAlloc() override;
226 bool addPreSched2() override;
227 bool addPreEmitPass() override;
231 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
232 return new ARMPassConfig(this, PM);
235 void ARMPassConfig::addIRPasses() {
236 const ARMSubtarget *Subtarget = &getARMSubtarget();
237 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
238 addPass(createAtomicExpandLoadLinkedPass(TM));
240 // Cmpxchg instructions are often used with a subsequent comparison to
241 // determine whether it succeeded. We can exploit existing control-flow in
242 // ldrex/strex loops to simplify this, but it needs tidying up.
243 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
244 addPass(createCFGSimplificationPass());
247 TargetPassConfig::addIRPasses();
250 bool ARMPassConfig::addPreISel() {
251 if (TM->getOptLevel() != CodeGenOpt::None)
252 addPass(createGlobalMergePass(TM));
257 bool ARMPassConfig::addInstSelector() {
258 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
260 const ARMSubtarget *Subtarget = &getARMSubtarget();
261 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
262 TM->Options.EnableFastISel)
263 addPass(createARMGlobalBaseRegPass());
267 bool ARMPassConfig::addPreRegAlloc() {
268 if (getOptLevel() != CodeGenOpt::None)
269 addPass(createARMLoadStoreOptimizationPass(true));
270 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
271 addPass(createMLxExpansionPass());
272 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
273 // enabled when NEON is available.
274 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
275 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
276 addPass(createA15SDOptimizerPass());
281 bool ARMPassConfig::addPreSched2() {
282 if (getOptLevel() != CodeGenOpt::None) {
283 addPass(createARMLoadStoreOptimizationPass());
284 printAndVerify("After ARM load / store optimizer");
286 if (getARMSubtarget().hasNEON())
287 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
290 // Expand some pseudo instructions into multiple instructions to allow
291 // proper scheduling.
292 addPass(createARMExpandPseudoPass());
294 if (getOptLevel() != CodeGenOpt::None) {
295 if (!getARMSubtarget().isThumb1Only()) {
296 // in v8, IfConversion depends on Thumb instruction widths
297 if (getARMSubtarget().restrictIT() &&
298 !getARMSubtarget().prefers32BitThumb())
299 addPass(createThumb2SizeReductionPass());
300 addPass(&IfConverterID);
303 if (getARMSubtarget().isThumb2())
304 addPass(createThumb2ITBlockPass());
309 bool ARMPassConfig::addPreEmitPass() {
310 if (getARMSubtarget().isThumb2()) {
311 if (!getARMSubtarget().prefers32BitThumb())
312 addPass(createThumb2SizeReductionPass());
314 // Constant island pass work on unbundled instructions.
315 addPass(&UnpackMachineBundlesID);
318 addPass(createARMOptimizeBarriersPass());
319 addPass(createARMConstantIslandPass());
324 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
325 JITCodeEmitter &JCE) {
326 // Machine code emitter pass for ARM.
327 PM.add(createARMJITCodeEmitterPass(*this, JCE));