1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Target/TargetRegistry.h"
24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
26 switch (TheTriple.getOS()) {
28 return new ARMMCAsmInfoDarwin();
30 return new ARMELFMCAsmInfo();
34 // This is duplicated code. Refactor this.
35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
36 MCContext &Ctx, TargetAsmBackend &TAB,
38 MCCodeEmitter *_Emitter,
41 switch (TheTriple.getOS()) {
43 return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
48 llvm_unreachable("ARM does not support Windows COFF format");
51 return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
55 extern "C" void LLVMInitializeARMTarget() {
56 // Register the target.
57 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
58 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
60 // Register the target asm info.
61 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
62 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
64 // Register the MC Code Emitter
65 TargetRegistry::RegisterCodeEmitter(TheARMTarget,
66 createARMMCCodeEmitter);
67 TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
68 createARMMCCodeEmitter);
70 // Register the asm backend.
71 TargetRegistry::RegisterAsmBackend(TheARMTarget,
73 TargetRegistry::RegisterAsmBackend(TheThumbTarget,
76 // Register the object streamer.
77 TargetRegistry::RegisterObjectStreamer(TheARMTarget,
79 TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
84 /// TargetMachine ctor - Create an ARM architecture model.
86 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
87 const std::string &TT,
88 const std::string &FS,
90 : LLVMTargetMachine(T, TT),
91 Subtarget(TT, FS, isThumb),
94 InstrItins(Subtarget.getInstrItineraryData())
96 DefRelocModel = getRelocationModel();
99 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
100 const std::string &FS)
101 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
102 DataLayout(Subtarget.isAPCS_ABI() ?
103 std::string("e-p:32:32-f64:32:64-i64:32:64-"
104 "v128:32:128-v64:32:64-n32") :
105 std::string("e-p:32:32-f64:64:64-i64:64:64-"
106 "v128:64:128-v64:64:64-n32")),
107 ELFWriterInfo(*this),
110 if (!Subtarget.hasARMOps())
111 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
112 "support ARM mode execution!");
115 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
116 const std::string &FS)
117 : ARMBaseTargetMachine(T, TT, FS, true),
118 InstrInfo(Subtarget.hasThumb2()
119 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
120 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
121 DataLayout(Subtarget.isAPCS_ABI() ?
122 std::string("e-p:32:32-f64:32:64-i64:32:64-"
123 "i16:16:32-i8:8:32-i1:8:32-"
124 "v128:32:128-v64:32:64-a:0:32-n32") :
125 std::string("e-p:32:32-f64:64:64-i64:64:64-"
126 "i16:16:32-i8:8:32-i1:8:32-"
127 "v128:64:128-v64:64:64-a:0:32-n32")),
128 ELFWriterInfo(*this),
133 // Pass Pipeline Configuration
134 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
135 CodeGenOpt::Level OptLevel) {
136 if (OptLevel != CodeGenOpt::None)
137 PM.add(createARMGlobalMergePass(getTargetLowering()));
142 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
143 CodeGenOpt::Level OptLevel) {
144 PM.add(createARMISelDag(*this, OptLevel));
148 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
149 CodeGenOpt::Level OptLevel) {
150 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
151 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
152 PM.add(createARMLoadStoreOptimizationPass(true));
157 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
158 CodeGenOpt::Level OptLevel) {
159 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
160 if (OptLevel != CodeGenOpt::None) {
161 if (!Subtarget.isThumb1Only())
162 PM.add(createARMLoadStoreOptimizationPass());
163 if (Subtarget.hasNEON())
164 PM.add(createNEONMoveFixPass());
167 // Expand some pseudo instructions into multiple instructions to allow
168 // proper scheduling.
169 PM.add(createARMExpandPseudoPass());
171 if (OptLevel != CodeGenOpt::None) {
172 if (!Subtarget.isThumb1Only())
173 PM.add(createIfConverterPass());
175 if (Subtarget.isThumb2())
176 PM.add(createThumb2ITBlockPass());
181 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
182 CodeGenOpt::Level OptLevel) {
183 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
184 PM.add(createThumb2SizeReductionPass());
186 PM.add(createARMConstantIslandPass());
190 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
191 CodeGenOpt::Level OptLevel,
192 JITCodeEmitter &JCE) {
193 // FIXME: Move this to TargetJITInfo!
194 if (DefRelocModel == Reloc::Default)
195 setRelocationModel(Reloc::Static);
197 // Machine code emitter pass for ARM.
198 PM.add(createARMJITCodeEmitterPass(*this, JCE));