1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableGlobalMerge("global-merge", cl::Hidden,
28 cl::desc("Enable global merge pass"),
32 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
33 cl::desc("Inhibit optimization of S->D register accesses on A15"),
36 extern "C" void LLVMInitializeARMTarget() {
37 // Register the target.
38 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
39 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
43 /// TargetMachine ctor - Create an ARM architecture model.
45 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
46 StringRef CPU, StringRef FS,
47 const TargetOptions &Options,
48 Reloc::Model RM, CodeModel::Model CM,
50 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
51 Subtarget(TT, CPU, FS, Options),
53 InstrItins(Subtarget.getInstrItineraryData()) {
54 // Default to soft float ABI
55 if (Options.FloatABIType == FloatABI::Default)
56 this->Options.FloatABIType = FloatABI::Soft;
59 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
60 // Add first the target-independent BasicTTI pass, then our ARM pass. This
61 // allows the ARM pass to delegate to the target independent layer when
63 PM.add(createBasicTargetTransformInfoPass(this));
64 PM.add(createARMTargetTransformInfoPass(this));
68 void ARMTargetMachine::anchor() { }
70 static std::string computeDataLayout(ARMSubtarget &ST) {
71 // Little endian. Pointers are 32 bits and aligned to 32 bits.
72 std::string Ret = "e-p:32:32";
74 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
77 Ret += "-i1:8:32-i8:8:32-i16:16:32";
79 // ABIs other than APC have 64 bit integers with natural alignment.
83 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
84 // bits, others to 64 bits. We always try to align to 64 bits.
88 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
89 // to 64. We always ty to give them natural alignment.
91 Ret += "-v64:32:64-v128:32:128";
93 Ret += "-v128:64:128";
95 // An aggregate of size 0 is ABI aligned to 0.
96 // FIXME: explain better what this means.
100 // Integer registers are 32 bits.
103 // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
104 if (ST.isAAPCS_ABI())
112 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
113 StringRef CPU, StringRef FS,
114 const TargetOptions &Options,
115 Reloc::Model RM, CodeModel::Model CM,
116 CodeGenOpt::Level OL)
117 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
118 InstrInfo(Subtarget),
119 DL(computeDataLayout(Subtarget)),
122 FrameLowering(Subtarget) {
124 if (!Subtarget.hasARMOps())
125 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
126 "support ARM mode execution!");
129 void ThumbTargetMachine::anchor() { }
131 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
132 StringRef CPU, StringRef FS,
133 const TargetOptions &Options,
134 Reloc::Model RM, CodeModel::Model CM,
135 CodeGenOpt::Level OL)
136 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
137 InstrInfo(Subtarget.hasThumb2()
138 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
139 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
140 DL(computeDataLayout(Subtarget)),
143 FrameLowering(Subtarget.hasThumb2()
144 ? new ARMFrameLowering(Subtarget)
145 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
150 /// ARM Code Generator Pass Configuration Options.
151 class ARMPassConfig : public TargetPassConfig {
153 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
154 : TargetPassConfig(TM, PM) {}
156 ARMBaseTargetMachine &getARMTargetMachine() const {
157 return getTM<ARMBaseTargetMachine>();
160 const ARMSubtarget &getARMSubtarget() const {
161 return *getARMTargetMachine().getSubtargetImpl();
164 virtual bool addPreISel();
165 virtual bool addInstSelector();
166 virtual bool addPreRegAlloc();
167 virtual bool addPreSched2();
168 virtual bool addPreEmitPass();
172 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
173 return new ARMPassConfig(this, PM);
176 bool ARMPassConfig::addPreISel() {
177 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
178 addPass(createGlobalMergePass(TM));
183 bool ARMPassConfig::addInstSelector() {
184 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
186 const ARMSubtarget *Subtarget = &getARMSubtarget();
187 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
188 TM->Options.EnableFastISel)
189 addPass(createARMGlobalBaseRegPass());
193 bool ARMPassConfig::addPreRegAlloc() {
194 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
195 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
196 addPass(createARMLoadStoreOptimizationPass(true));
197 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
198 addPass(createMLxExpansionPass());
199 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
200 // enabled when NEON is available.
201 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
202 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
203 addPass(createA15SDOptimizerPass());
208 bool ARMPassConfig::addPreSched2() {
209 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
210 if (getOptLevel() != CodeGenOpt::None) {
211 if (!getARMSubtarget().isThumb1Only()) {
212 addPass(createARMLoadStoreOptimizationPass());
213 printAndVerify("After ARM load / store optimizer");
215 if (getARMSubtarget().hasNEON())
216 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
219 // Expand some pseudo instructions into multiple instructions to allow
220 // proper scheduling.
221 addPass(createARMExpandPseudoPass());
223 if (getOptLevel() != CodeGenOpt::None) {
224 if (!getARMSubtarget().isThumb1Only()) {
225 // in v8, IfConversion depends on Thumb instruction widths
226 if (getARMSubtarget().restrictIT() &&
227 !getARMSubtarget().prefers32BitThumb())
228 addPass(createThumb2SizeReductionPass());
229 addPass(&IfConverterID);
232 if (getARMSubtarget().isThumb2())
233 addPass(createThumb2ITBlockPass());
238 bool ARMPassConfig::addPreEmitPass() {
239 if (getARMSubtarget().isThumb2()) {
240 if (!getARMSubtarget().prefers32BitThumb())
241 addPass(createThumb2SizeReductionPass());
243 // Constant island pass work on unbundled instructions.
244 addPass(&UnpackMachineBundlesID);
247 addPass(createARMConstantIslandPass());
252 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
253 JITCodeEmitter &JCE) {
254 // Machine code emitter pass for ARM.
255 PM.add(createARMJITCodeEmitterPass(*this, JCE));