1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMTargetAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Target/TargetRegistry.h"
26 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
27 cl::desc("Disable load store optimization pass"));
28 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
29 cl::desc("Disable if-conversion pass"));
31 extern "C" void LLVMInitializeARMTarget() {
32 // Register the target.
33 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
34 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
37 /// TargetMachine ctor - Create an ARM architecture model.
39 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
41 const std::string &FS,
43 : LLVMTargetMachine(T),
44 Subtarget(M, FS, isThumb),
47 InstrItins(Subtarget.getInstrItineraryData()) {
48 DefRelocModel = getRelocationModel();
51 ARMTargetMachine::ARMTargetMachine(const Target &T, const Module &M,
52 const std::string &FS)
53 : ARMBaseTargetMachine(T, M, FS, false), InstrInfo(Subtarget),
54 DataLayout(Subtarget.isAPCS_ABI() ?
55 std::string("e-p:32:32-f64:32:32-i64:32:32") :
56 std::string("e-p:32:32-f64:64:64-i64:64:64")),
60 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Module &M,
61 const std::string &FS)
62 : ARMBaseTargetMachine(T, M, FS, true),
63 DataLayout(Subtarget.isAPCS_ABI() ?
64 std::string("e-p:32:32-f64:32:32-i64:32:32-"
65 "i16:16:32-i8:8:32-i1:8:32-a:0:32") :
66 std::string("e-p:32:32-f64:64:64-i64:64:64-"
67 "i16:16:32-i8:8:32-i1:8:32-a:0:32")),
69 // Create the approriate type of Thumb InstrInfo
70 if (Subtarget.hasThumb2())
71 InstrInfo = new Thumb2InstrInfo(Subtarget);
73 InstrInfo = new Thumb1InstrInfo(Subtarget);
77 const TargetAsmInfo *ARMBaseTargetMachine::createTargetAsmInfo() const {
78 switch (Subtarget.TargetType) {
79 default: llvm_unreachable("Unknown ARM subtarget kind");
80 case ARMSubtarget::isDarwin:
81 return new ARMDarwinTargetAsmInfo(*this);
82 case ARMSubtarget::isELF:
83 return new ARMELFTargetAsmInfo(*this);
88 // Pass Pipeline Configuration
89 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
90 CodeGenOpt::Level OptLevel) {
91 PM.add(createARMISelDag(*this));
95 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
96 CodeGenOpt::Level OptLevel) {
97 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
98 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
99 PM.add(createARMLoadStoreOptimizationPass(true));
103 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
104 CodeGenOpt::Level OptLevel) {
105 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
106 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
107 PM.add(createARMLoadStoreOptimizationPass());
109 if (OptLevel != CodeGenOpt::None &&
110 !DisableIfConversion && !Subtarget.isThumb())
111 PM.add(createIfConverterPass());
113 if (Subtarget.isThumb2())
114 PM.add(createThumb2ITBlockPass());
116 PM.add(createARMConstantIslandPass());
120 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
121 CodeGenOpt::Level OptLevel,
122 MachineCodeEmitter &MCE) {
123 // FIXME: Move this to TargetJITInfo!
124 if (DefRelocModel == Reloc::Default)
125 setRelocationModel(Reloc::Static);
127 // Machine code emitter pass for ARM.
128 PM.add(createARMCodeEmitterPass(*this, MCE));
132 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
133 CodeGenOpt::Level OptLevel,
134 JITCodeEmitter &JCE) {
135 // FIXME: Move this to TargetJITInfo!
136 if (DefRelocModel == Reloc::Default)
137 setRelocationModel(Reloc::Static);
139 // Machine code emitter pass for ARM.
140 PM.add(createARMJITCodeEmitterPass(*this, JCE));
144 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
145 CodeGenOpt::Level OptLevel,
146 ObjectCodeEmitter &OCE) {
147 // FIXME: Move this to TargetJITInfo!
148 if (DefRelocModel == Reloc::Default)
149 setRelocationModel(Reloc::Static);
151 // Machine code emitter pass for ARM.
152 PM.add(createARMObjectCodeEmitterPass(*this, OCE));
156 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
157 CodeGenOpt::Level OptLevel,
158 MachineCodeEmitter &MCE) {
159 // Machine code emitter pass for ARM.
160 PM.add(createARMCodeEmitterPass(*this, MCE));
164 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
165 CodeGenOpt::Level OptLevel,
166 JITCodeEmitter &JCE) {
167 // Machine code emitter pass for ARM.
168 PM.add(createARMJITCodeEmitterPass(*this, JCE));
172 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
173 CodeGenOpt::Level OptLevel,
174 ObjectCodeEmitter &OCE) {
175 // Machine code emitter pass for ARM.
176 PM.add(createARMObjectCodeEmitterPass(*this, OCE));