1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMTargetAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetRegistry.h"
25 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
26 cl::desc("Disable load store optimization pass"));
27 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
28 cl::desc("Disable if-conversion pass"));
30 extern "C" void LLVMInitializeARMTarget() {
31 // Register the target.
32 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
33 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
36 /// TargetMachine ctor - Create an ARM architecture model.
38 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
39 const std::string &TT,
40 const std::string &FS,
42 : LLVMTargetMachine(T),
43 Subtarget(TT, FS, isThumb),
46 InstrItins(Subtarget.getInstrItineraryData()) {
47 DefRelocModel = getRelocationModel();
50 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
51 const std::string &FS)
52 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
53 DataLayout(Subtarget.isAPCS_ABI() ?
54 std::string("e-p:32:32-f64:32:32-i64:32:32") :
55 std::string("e-p:32:32-f64:64:64-i64:64:64")),
59 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
60 const std::string &FS)
61 : ARMBaseTargetMachine(T, TT, FS, true),
62 DataLayout(Subtarget.isAPCS_ABI() ?
63 std::string("e-p:32:32-f64:32:32-i64:32:32-"
64 "i16:16:32-i8:8:32-i1:8:32-a:0:32") :
65 std::string("e-p:32:32-f64:64:64-i64:64:64-"
66 "i16:16:32-i8:8:32-i1:8:32-a:0:32")),
68 // Create the approriate type of Thumb InstrInfo
69 if (Subtarget.hasThumb2())
70 InstrInfo = new Thumb2InstrInfo(Subtarget);
72 InstrInfo = new Thumb1InstrInfo(Subtarget);
76 const TargetAsmInfo *ARMBaseTargetMachine::createTargetAsmInfo() const {
77 switch (Subtarget.TargetType) {
78 default: llvm_unreachable("Unknown ARM subtarget kind");
79 case ARMSubtarget::isDarwin:
80 return new ARMDarwinTargetAsmInfo();
81 case ARMSubtarget::isELF:
82 return new ARMELFTargetAsmInfo();
87 // Pass Pipeline Configuration
88 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
89 CodeGenOpt::Level OptLevel) {
90 PM.add(createARMISelDag(*this));
94 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
95 CodeGenOpt::Level OptLevel) {
96 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
97 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
98 PM.add(createARMLoadStoreOptimizationPass(true));
102 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
103 CodeGenOpt::Level OptLevel) {
104 // FIXME: temporarily disabling load / store optimization pass for Thumb1 mode.
105 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti &&
106 !Subtarget.isThumb1Only())
107 PM.add(createARMLoadStoreOptimizationPass());
109 if (OptLevel != CodeGenOpt::None &&
110 !DisableIfConversion && !Subtarget.isThumb())
111 PM.add(createIfConverterPass());
113 if (Subtarget.isThumb2())
114 PM.add(createThumb2ITBlockPass());
116 PM.add(createARMConstantIslandPass());
120 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
121 CodeGenOpt::Level OptLevel,
122 MachineCodeEmitter &MCE) {
123 // FIXME: Move this to TargetJITInfo!
124 if (DefRelocModel == Reloc::Default)
125 setRelocationModel(Reloc::Static);
127 // Machine code emitter pass for ARM.
128 PM.add(createARMCodeEmitterPass(*this, MCE));
132 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
133 CodeGenOpt::Level OptLevel,
134 JITCodeEmitter &JCE) {
135 // FIXME: Move this to TargetJITInfo!
136 if (DefRelocModel == Reloc::Default)
137 setRelocationModel(Reloc::Static);
139 // Machine code emitter pass for ARM.
140 PM.add(createARMJITCodeEmitterPass(*this, JCE));
144 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
145 CodeGenOpt::Level OptLevel,
146 ObjectCodeEmitter &OCE) {
147 // FIXME: Move this to TargetJITInfo!
148 if (DefRelocModel == Reloc::Default)
149 setRelocationModel(Reloc::Static);
151 // Machine code emitter pass for ARM.
152 PM.add(createARMObjectCodeEmitterPass(*this, OCE));
156 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
157 CodeGenOpt::Level OptLevel,
158 MachineCodeEmitter &MCE) {
159 // Machine code emitter pass for ARM.
160 PM.add(createARMCodeEmitterPass(*this, MCE));
164 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
165 CodeGenOpt::Level OptLevel,
166 JITCodeEmitter &JCE) {
167 // Machine code emitter pass for ARM.
168 PM.add(createARMJITCodeEmitterPass(*this, JCE));
172 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
173 CodeGenOpt::Level OptLevel,
174 ObjectCodeEmitter &OCE) {
175 // Machine code emitter pass for ARM.
176 PM.add(createARMObjectCodeEmitterPass(*this, OCE));