1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMFrameLowering.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/FormattedStream.h"
20 #include "llvm/Support/TargetRegistry.h"
21 #include "llvm/Target/TargetOptions.h"
24 extern "C" void LLVMInitializeARMTarget() {
25 // Register the target.
26 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
27 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
30 /// TargetMachine ctor - Create an ARM architecture model.
32 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
33 StringRef CPU, StringRef FS,
34 Reloc::Model RM, CodeModel::Model CM)
35 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
36 Subtarget(TT, CPU, FS),
38 InstrItins(Subtarget.getInstrItineraryData()) {
39 // Default to soft float ABI
40 if (FloatABIType == FloatABI::Default)
41 FloatABIType = FloatABI::Soft;
44 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
45 StringRef CPU, StringRef FS,
46 Reloc::Model RM, CodeModel::Model CM)
47 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
48 DataLayout(Subtarget.isAPCS_ABI() ?
49 std::string("e-p:32:32-f64:32:64-i64:32:64-"
50 "v128:32:128-v64:32:64-n32") :
51 std::string("e-p:32:32-f64:64:64-i64:64:64-"
52 "v128:64:128-v64:64:64-n32")),
56 FrameLowering(Subtarget) {
57 if (!Subtarget.hasARMOps())
58 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
59 "support ARM mode execution!");
62 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
63 StringRef CPU, StringRef FS,
64 Reloc::Model RM, CodeModel::Model CM)
65 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
66 InstrInfo(Subtarget.hasThumb2()
67 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
68 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
69 DataLayout(Subtarget.isAPCS_ABI() ?
70 std::string("e-p:32:32-f64:32:64-i64:32:64-"
71 "i16:16:32-i8:8:32-i1:8:32-"
72 "v128:32:128-v64:32:64-a:0:32-n32") :
73 std::string("e-p:32:32-f64:64:64-i64:64:64-"
74 "i16:16:32-i8:8:32-i1:8:32-"
75 "v128:64:128-v64:64:64-a:0:32-n32")),
79 FrameLowering(Subtarget.hasThumb2()
80 ? new ARMFrameLowering(Subtarget)
81 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
84 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
85 CodeGenOpt::Level OptLevel) {
86 if (OptLevel != CodeGenOpt::None)
87 PM.add(createARMGlobalMergePass(getTargetLowering()));
92 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
93 CodeGenOpt::Level OptLevel) {
94 PM.add(createARMISelDag(*this, OptLevel));
98 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
99 CodeGenOpt::Level OptLevel) {
100 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
101 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
102 PM.add(createARMLoadStoreOptimizationPass(true));
103 if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
104 PM.add(createMLxExpansionPass());
109 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
110 CodeGenOpt::Level OptLevel) {
111 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
112 if (OptLevel != CodeGenOpt::None) {
113 if (!Subtarget.isThumb1Only())
114 PM.add(createARMLoadStoreOptimizationPass());
115 if (Subtarget.hasNEON())
116 PM.add(createNEONMoveFixPass());
119 // Expand some pseudo instructions into multiple instructions to allow
120 // proper scheduling.
121 PM.add(createARMExpandPseudoPass());
123 if (OptLevel != CodeGenOpt::None) {
124 if (!Subtarget.isThumb1Only())
125 PM.add(createIfConverterPass());
127 if (Subtarget.isThumb2())
128 PM.add(createThumb2ITBlockPass());
133 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
134 CodeGenOpt::Level OptLevel) {
135 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
136 PM.add(createThumb2SizeReductionPass());
138 PM.add(createARMConstantIslandPass());
142 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
143 CodeGenOpt::Level OptLevel,
144 JITCodeEmitter &JCE) {
145 // Machine code emitter pass for ARM.
146 PM.add(createARMJITCodeEmitterPass(*this, JCE));