1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "ARMTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/PassManager.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/FormattedStream.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Transforms/Scalar.h"
29 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
30 cl::desc("Inhibit optimization of S->D register accesses on A15"),
34 EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
35 cl::desc("Run SimplifyCFG after expanding atomic operations"
36 " to make use of cmpxchg flow-based information"),
39 extern "C" void LLVMInitializeARMTarget() {
40 // Register the target.
41 RegisterTargetMachine<ARMLETargetMachine> X(TheARMLETarget);
42 RegisterTargetMachine<ARMBETargetMachine> Y(TheARMBETarget);
43 RegisterTargetMachine<ThumbLETargetMachine> A(TheThumbLETarget);
44 RegisterTargetMachine<ThumbBETargetMachine> B(TheThumbBETarget);
47 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
48 if (TT.isOSBinFormatMachO())
49 return make_unique<TargetLoweringObjectFileMachO>();
51 return make_unique<TargetLoweringObjectFileCOFF>();
52 return make_unique<ARMElfTargetObjectFile>();
55 static ARMBaseTargetMachine::ARMABI
56 computeTargetABI(const Triple &TT, StringRef CPU,
57 const TargetOptions &Options) {
58 if (Options.getABIName().startswith("aapcs"))
59 return ARMBaseTargetMachine::ARM_ABI_AAPCS;
60 else if (Options.getABIName().startswith("apcs"))
61 return ARMBaseTargetMachine::ARM_ABI_APCS;
63 assert(Options.getABIName().empty() && "Unknown target-abi option!");
65 ARMBaseTargetMachine::ARMABI TargetABI =
66 ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
68 // FIXME: This is duplicated code from the front end and should be unified.
69 if (TT.isOSBinFormatMachO()) {
70 if (TT.getEnvironment() == llvm::Triple::EABI ||
71 (TT.getOS() == llvm::Triple::UnknownOS &&
72 TT.getObjectFormat() == llvm::Triple::MachO) ||
73 CPU.startswith("cortex-m")) {
74 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
76 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
78 } else if (TT.isOSWindows()) {
79 // FIXME: this is invalid for WindowsCE
80 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
82 // Select the default based on the platform.
83 switch (TT.getEnvironment()) {
84 case llvm::Triple::Android:
85 case llvm::Triple::GNUEABI:
86 case llvm::Triple::GNUEABIHF:
87 case llvm::Triple::EABIHF:
88 case llvm::Triple::EABI:
89 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
91 case llvm::Triple::GNU:
92 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
95 if (TT.getOS() == llvm::Triple::NetBSD)
96 TargetABI = ARMBaseTargetMachine::ARM_ABI_APCS;
98 TargetABI = ARMBaseTargetMachine::ARM_ABI_AAPCS;
106 /// TargetMachine ctor - Create an ARM architecture model.
108 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
109 StringRef CPU, StringRef FS,
110 const TargetOptions &Options,
111 Reloc::Model RM, CodeModel::Model CM,
112 CodeGenOpt::Level OL, bool isLittle)
113 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
114 TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
115 TLOF(createTLOF(Triple(getTargetTriple()))),
116 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) {
118 // Default to triple-appropriate float ABI
119 if (Options.FloatABIType == FloatABI::Default)
120 this->Options.FloatABIType =
121 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
124 ARMBaseTargetMachine::~ARMBaseTargetMachine() {}
127 ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
128 AttributeSet FnAttrs = F.getAttributes();
130 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
132 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
134 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
135 ? CPUAttr.getValueAsString().str()
137 std::string FS = !FSAttr.hasAttribute(Attribute::None)
138 ? FSAttr.getValueAsString().str()
141 // FIXME: This is related to the code below to reset the target options,
142 // we need to know whether or not the soft float flag is set on the
143 // function before we can generate a subtarget. We also need to use
144 // it as a key for the subtarget since that can be the only difference
145 // between two functions.
147 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float");
148 bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)
149 ? SFAttr.getValueAsString() == "true"
150 : Options.UseSoftFloat;
152 auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"
153 : "use-soft-float=false")];
155 // This needs to be done before we create a new subtarget since any
156 // creation will depend on the TM and the code generation flags on the
157 // function that reside in TargetOptions.
158 resetTargetOptions(F);
159 I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
164 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
165 // Add first the target-independent BasicTTI pass, then our ARM pass. This
166 // allows the ARM pass to delegate to the target independent layer when
168 PM.add(createBasicTargetTransformInfoPass(this));
169 PM.add(createARMTargetTransformInfoPass(this));
173 void ARMTargetMachine::anchor() { }
175 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU,
176 StringRef FS, const TargetOptions &Options,
177 Reloc::Model RM, CodeModel::Model CM,
178 CodeGenOpt::Level OL, bool isLittle)
179 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) {
181 if (!Subtarget.hasARMOps())
182 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
183 "support ARM mode execution!");
186 void ARMLETargetMachine::anchor() { }
188 ARMLETargetMachine::ARMLETargetMachine(const Target &T, StringRef TT,
189 StringRef CPU, StringRef FS,
190 const TargetOptions &Options,
191 Reloc::Model RM, CodeModel::Model CM,
192 CodeGenOpt::Level OL)
193 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
195 void ARMBETargetMachine::anchor() { }
197 ARMBETargetMachine::ARMBETargetMachine(const Target &T, StringRef TT,
198 StringRef CPU, StringRef FS,
199 const TargetOptions &Options,
200 Reloc::Model RM, CodeModel::Model CM,
201 CodeGenOpt::Level OL)
202 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
204 void ThumbTargetMachine::anchor() { }
206 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
207 StringRef CPU, StringRef FS,
208 const TargetOptions &Options,
209 Reloc::Model RM, CodeModel::Model CM,
210 CodeGenOpt::Level OL, bool isLittle)
211 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL,
216 void ThumbLETargetMachine::anchor() { }
218 ThumbLETargetMachine::ThumbLETargetMachine(const Target &T, StringRef TT,
219 StringRef CPU, StringRef FS,
220 const TargetOptions &Options,
221 Reloc::Model RM, CodeModel::Model CM,
222 CodeGenOpt::Level OL)
223 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
225 void ThumbBETargetMachine::anchor() { }
227 ThumbBETargetMachine::ThumbBETargetMachine(const Target &T, StringRef TT,
228 StringRef CPU, StringRef FS,
229 const TargetOptions &Options,
230 Reloc::Model RM, CodeModel::Model CM,
231 CodeGenOpt::Level OL)
232 : ThumbTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
235 /// ARM Code Generator Pass Configuration Options.
236 class ARMPassConfig : public TargetPassConfig {
238 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
239 : TargetPassConfig(TM, PM) {}
241 ARMBaseTargetMachine &getARMTargetMachine() const {
242 return getTM<ARMBaseTargetMachine>();
245 const ARMSubtarget &getARMSubtarget() const {
246 return *getARMTargetMachine().getSubtargetImpl();
249 void addIRPasses() override;
250 bool addPreISel() override;
251 bool addInstSelector() override;
252 void addPreRegAlloc() override;
253 void addPreSched2() override;
254 void addPreEmitPass() override;
258 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
259 return new ARMPassConfig(this, PM);
262 void ARMPassConfig::addIRPasses() {
263 if (TM->Options.ThreadModel == ThreadModel::Single)
264 addPass(createLowerAtomicPass());
266 addPass(createAtomicExpandPass(TM));
268 // Cmpxchg instructions are often used with a subsequent comparison to
269 // determine whether it succeeded. We can exploit existing control-flow in
270 // ldrex/strex loops to simplify this, but it needs tidying up.
271 const ARMSubtarget *Subtarget = &getARMSubtarget();
272 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only())
273 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
274 addPass(createCFGSimplificationPass());
276 TargetPassConfig::addIRPasses();
279 bool ARMPassConfig::addPreISel() {
280 if (TM->getOptLevel() != CodeGenOpt::None)
281 addPass(createGlobalMergePass(TM));
286 bool ARMPassConfig::addInstSelector() {
287 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
289 const ARMSubtarget *Subtarget = &getARMSubtarget();
290 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
291 TM->Options.EnableFastISel)
292 addPass(createARMGlobalBaseRegPass());
296 void ARMPassConfig::addPreRegAlloc() {
297 if (getOptLevel() != CodeGenOpt::None)
298 addPass(createARMLoadStoreOptimizationPass(true));
299 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
300 addPass(createMLxExpansionPass());
301 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
302 // enabled when NEON is available.
303 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
304 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
305 addPass(createA15SDOptimizerPass());
309 void ARMPassConfig::addPreSched2() {
310 if (getOptLevel() != CodeGenOpt::None) {
311 addPass(createARMLoadStoreOptimizationPass());
313 if (getARMSubtarget().hasNEON())
314 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
317 // Expand some pseudo instructions into multiple instructions to allow
318 // proper scheduling.
319 addPass(createARMExpandPseudoPass());
321 if (getOptLevel() != CodeGenOpt::None) {
322 if (!getARMSubtarget().isThumb1Only()) {
323 // in v8, IfConversion depends on Thumb instruction widths
324 if (getARMSubtarget().restrictIT() &&
325 !getARMSubtarget().prefers32BitThumb())
326 addPass(createThumb2SizeReductionPass());
327 addPass(&IfConverterID);
330 if (getARMSubtarget().isThumb2())
331 addPass(createThumb2ITBlockPass());
334 void ARMPassConfig::addPreEmitPass() {
335 if (getARMSubtarget().isThumb2()) {
336 if (!getARMSubtarget().prefers32BitThumb())
337 addPass(createThumb2SizeReductionPass());
339 // Constant island pass work on unbundled instructions.
340 addPass(&UnpackMachineBundlesID);
343 addPass(createARMOptimizeBarriersPass());
344 addPass(createARMConstantIslandPass());