1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMTargetAsmInfo.h"
15 #include "ARMFrameInfo.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetRegistry.h"
25 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
26 cl::desc("Disable load store optimization pass"));
27 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
28 cl::desc("Disable if-conversion pass"));
30 static const TargetAsmInfo *createTargetAsmInfo(const Target &T,
31 const StringRef &TT) {
33 switch (TheTriple.getOS()) {
35 return new ARMDarwinTargetAsmInfo();
37 return new ARMELFTargetAsmInfo();
42 extern "C" void LLVMInitializeARMTarget() {
43 // Register the target.
44 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
45 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
47 // Register the target asm info.
48 RegisterAsmInfoFn A(TheARMTarget, createTargetAsmInfo);
49 RegisterAsmInfoFn B(TheThumbTarget, createTargetAsmInfo);
52 /// TargetMachine ctor - Create an ARM architecture model.
54 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
55 const std::string &TT,
56 const std::string &FS,
58 : LLVMTargetMachine(T, TT),
59 Subtarget(TT, FS, isThumb),
62 InstrItins(Subtarget.getInstrItineraryData()) {
63 DefRelocModel = getRelocationModel();
66 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
67 const std::string &FS)
68 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
69 DataLayout(Subtarget.isAPCS_ABI() ?
70 std::string("e-p:32:32-f64:32:32-i64:32:32") :
71 std::string("e-p:32:32-f64:64:64-i64:64:64")),
75 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
76 const std::string &FS)
77 : ARMBaseTargetMachine(T, TT, FS, true),
78 DataLayout(Subtarget.isAPCS_ABI() ?
79 std::string("e-p:32:32-f64:32:32-i64:32:32-"
80 "i16:16:32-i8:8:32-i1:8:32-a:0:32") :
81 std::string("e-p:32:32-f64:64:64-i64:64:64-"
82 "i16:16:32-i8:8:32-i1:8:32-a:0:32")),
84 // Create the approriate type of Thumb InstrInfo
85 if (Subtarget.hasThumb2())
86 InstrInfo = new Thumb2InstrInfo(Subtarget);
88 InstrInfo = new Thumb1InstrInfo(Subtarget);
93 // Pass Pipeline Configuration
94 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
95 CodeGenOpt::Level OptLevel) {
96 PM.add(createARMISelDag(*this));
100 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
101 CodeGenOpt::Level OptLevel) {
102 if (Subtarget.hasNEON())
103 PM.add(createNEONPreAllocPass());
105 // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
106 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
107 PM.add(createARMLoadStoreOptimizationPass(true));
111 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
112 CodeGenOpt::Level OptLevel) {
113 // FIXME: temporarily disabling load / store optimization pass for Thumb1 mode.
114 if (OptLevel != CodeGenOpt::None && !DisableLdStOpti &&
115 !Subtarget.isThumb1Only())
116 PM.add(createARMLoadStoreOptimizationPass());
118 if (OptLevel != CodeGenOpt::None &&
119 !DisableIfConversion && !Subtarget.isThumb())
120 PM.add(createIfConverterPass());
122 if (Subtarget.isThumb2()) {
123 PM.add(createThumb2ITBlockPass());
124 PM.add(createThumb2SizeReductionPass());
127 PM.add(createARMConstantIslandPass());
131 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
132 CodeGenOpt::Level OptLevel,
133 MachineCodeEmitter &MCE) {
134 // FIXME: Move this to TargetJITInfo!
135 if (DefRelocModel == Reloc::Default)
136 setRelocationModel(Reloc::Static);
138 // Machine code emitter pass for ARM.
139 PM.add(createARMCodeEmitterPass(*this, MCE));
143 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
144 CodeGenOpt::Level OptLevel,
145 JITCodeEmitter &JCE) {
146 // FIXME: Move this to TargetJITInfo!
147 if (DefRelocModel == Reloc::Default)
148 setRelocationModel(Reloc::Static);
150 // Machine code emitter pass for ARM.
151 PM.add(createARMJITCodeEmitterPass(*this, JCE));
155 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
156 CodeGenOpt::Level OptLevel,
157 ObjectCodeEmitter &OCE) {
158 // FIXME: Move this to TargetJITInfo!
159 if (DefRelocModel == Reloc::Default)
160 setRelocationModel(Reloc::Static);
162 // Machine code emitter pass for ARM.
163 PM.add(createARMObjectCodeEmitterPass(*this, OCE));
167 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
168 CodeGenOpt::Level OptLevel,
169 MachineCodeEmitter &MCE) {
170 // Machine code emitter pass for ARM.
171 PM.add(createARMCodeEmitterPass(*this, MCE));
175 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
176 CodeGenOpt::Level OptLevel,
177 JITCodeEmitter &JCE) {
178 // Machine code emitter pass for ARM.
179 PM.add(createARMJITCodeEmitterPass(*this, JCE));
183 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
184 CodeGenOpt::Level OptLevel,
185 ObjectCodeEmitter &OCE) {
186 // Machine code emitter pass for ARM.
187 PM.add(createARMObjectCodeEmitterPass(*this, OCE));