1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMFrameLowering.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
26 EnableGlobalMerge("global-merge", cl::Hidden,
27 cl::desc("Enable global merge pass"),
30 extern "C" void LLVMInitializeARMTarget() {
31 // Register the target.
32 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
33 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
36 /// TargetMachine ctor - Create an ARM architecture model.
38 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
39 StringRef CPU, StringRef FS,
40 Reloc::Model RM, CodeModel::Model CM)
41 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
42 Subtarget(TT, CPU, FS),
44 InstrItins(Subtarget.getInstrItineraryData()) {
45 // Default to soft float ABI
46 if (FloatABIType == FloatABI::Default)
47 FloatABIType = FloatABI::Soft;
50 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
51 StringRef CPU, StringRef FS,
52 Reloc::Model RM, CodeModel::Model CM)
53 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM), InstrInfo(Subtarget),
54 DataLayout(Subtarget.isAPCS_ABI() ?
55 std::string("e-p:32:32-f64:32:64-i64:32:64-"
56 "v128:32:128-v64:32:64-n32") :
57 std::string("e-p:32:32-f64:64:64-i64:64:64-"
58 "v128:64:128-v64:64:64-n32")),
62 FrameLowering(Subtarget) {
63 if (!Subtarget.hasARMOps())
64 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
65 "support ARM mode execution!");
68 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS,
70 Reloc::Model RM, CodeModel::Model CM)
71 : ARMBaseTargetMachine(T, TT, CPU, FS, RM, CM),
72 InstrInfo(Subtarget.hasThumb2()
73 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
74 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
75 DataLayout(Subtarget.isAPCS_ABI() ?
76 std::string("e-p:32:32-f64:32:64-i64:32:64-"
77 "i16:16:32-i8:8:32-i1:8:32-"
78 "v128:32:128-v64:32:64-a:0:32-n32") :
79 std::string("e-p:32:32-f64:64:64-i64:64:64-"
80 "i16:16:32-i8:8:32-i1:8:32-"
81 "v128:64:128-v64:64:64-a:0:32-n32")),
85 FrameLowering(Subtarget.hasThumb2()
86 ? new ARMFrameLowering(Subtarget)
87 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
90 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
91 CodeGenOpt::Level OptLevel) {
92 if (OptLevel != CodeGenOpt::None && EnableGlobalMerge)
93 PM.add(createARMGlobalMergePass(getTargetLowering()));
98 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
99 CodeGenOpt::Level OptLevel) {
100 PM.add(createARMISelDag(*this, OptLevel));
104 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
105 CodeGenOpt::Level OptLevel) {
106 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
107 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
108 PM.add(createARMLoadStoreOptimizationPass(true));
109 if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
110 PM.add(createMLxExpansionPass());
111 if (getMCAsmInfo()->getExceptionHandlingType() == ExceptionHandling::SjLj)
112 createARMSjLjLoweringPass();
116 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
117 CodeGenOpt::Level OptLevel) {
118 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
119 if (OptLevel != CodeGenOpt::None) {
120 if (!Subtarget.isThumb1Only())
121 PM.add(createARMLoadStoreOptimizationPass());
122 if (Subtarget.hasNEON())
123 PM.add(createNEONMoveFixPass());
126 // Expand some pseudo instructions into multiple instructions to allow
127 // proper scheduling.
128 PM.add(createARMExpandPseudoPass());
130 if (OptLevel != CodeGenOpt::None) {
131 if (!Subtarget.isThumb1Only())
132 PM.add(createIfConverterPass());
134 if (Subtarget.isThumb2())
135 PM.add(createThumb2ITBlockPass());
140 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
141 CodeGenOpt::Level OptLevel) {
142 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
143 PM.add(createThumb2SizeReductionPass());
145 PM.add(createARMConstantIslandPass());
149 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
150 CodeGenOpt::Level OptLevel,
151 JITCodeEmitter &JCE) {
152 // Machine code emitter pass for ARM.
153 PM.add(createARMJITCodeEmitterPass(*this, JCE));