1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMFrameLowering.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableGlobalMerge("global-merge", cl::Hidden,
28 cl::desc("Enable global merge pass"),
31 extern "C" void LLVMInitializeARMTarget() {
32 // Register the target.
33 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
34 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
38 /// TargetMachine ctor - Create an ARM architecture model.
40 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
46 Subtarget(TT, CPU, FS),
48 InstrItins(Subtarget.getInstrItineraryData()) {
49 // Default to soft float ABI
50 if (Options.FloatABIType == FloatABI::Default)
51 this->Options.FloatABIType = FloatABI::Soft;
54 void ARMTargetMachine::anchor() { }
56 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
57 StringRef CPU, StringRef FS,
58 const TargetOptions &Options,
59 Reloc::Model RM, CodeModel::Model CM,
61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
63 DL(Subtarget.isAPCS_ABI() ?
64 std::string("e-p:32:32-f64:32:64-i64:32:64-"
65 "v128:32:128-v64:32:64-n32-S32") :
66 Subtarget.isAAPCS_ABI() ?
67 std::string("e-p:32:32-f64:64:64-i64:64:64-"
68 "v128:64:128-v64:64:64-n32-S64") :
69 std::string("e-p:32:32-f64:64:64-i64:64:64-"
70 "v128:64:128-v64:64:64-n32-S32")),
74 FrameLowering(Subtarget),
75 STTI(&TLInfo), VTTI(&TLInfo) {
76 if (!Subtarget.hasARMOps())
77 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
78 "support ARM mode execution!");
81 void ThumbTargetMachine::anchor() { }
83 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
84 StringRef CPU, StringRef FS,
85 const TargetOptions &Options,
86 Reloc::Model RM, CodeModel::Model CM,
88 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
89 InstrInfo(Subtarget.hasThumb2()
90 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
91 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
92 DL(Subtarget.isAPCS_ABI() ?
93 std::string("e-p:32:32-f64:32:64-i64:32:64-"
94 "i16:16:32-i8:8:32-i1:8:32-"
95 "v128:32:128-v64:32:64-a:0:32-n32-S32") :
96 Subtarget.isAAPCS_ABI() ?
97 std::string("e-p:32:32-f64:64:64-i64:64:64-"
98 "i16:16:32-i8:8:32-i1:8:32-"
99 "v128:64:128-v64:64:64-a:0:32-n32-S64") :
100 std::string("e-p:32:32-f64:64:64-i64:64:64-"
101 "i16:16:32-i8:8:32-i1:8:32-"
102 "v128:64:128-v64:64:64-a:0:32-n32-S32")),
103 ELFWriterInfo(*this),
106 FrameLowering(Subtarget.hasThumb2()
107 ? new ARMFrameLowering(Subtarget)
108 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)),
109 STTI(&TLInfo), VTTI(&TLInfo) {
113 /// ARM Code Generator Pass Configuration Options.
114 class ARMPassConfig : public TargetPassConfig {
116 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
117 : TargetPassConfig(TM, PM) {}
119 ARMBaseTargetMachine &getARMTargetMachine() const {
120 return getTM<ARMBaseTargetMachine>();
123 const ARMSubtarget &getARMSubtarget() const {
124 return *getARMTargetMachine().getSubtargetImpl();
127 virtual bool addPreISel();
128 virtual bool addInstSelector();
129 virtual bool addPreRegAlloc();
130 virtual bool addPreSched2();
131 virtual bool addPreEmitPass();
135 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
136 return new ARMPassConfig(this, PM);
139 bool ARMPassConfig::addPreISel() {
140 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
141 addPass(createGlobalMergePass(TM->getTargetLowering()));
146 bool ARMPassConfig::addInstSelector() {
147 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
149 const ARMSubtarget *Subtarget = &getARMSubtarget();
150 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
151 TM->Options.EnableFastISel)
152 addPass(createARMGlobalBaseRegPass());
156 bool ARMPassConfig::addPreRegAlloc() {
157 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
158 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
159 addPass(createARMLoadStoreOptimizationPass(true));
160 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isLikeA9())
161 addPass(createMLxExpansionPass());
165 bool ARMPassConfig::addPreSched2() {
166 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
167 if (getOptLevel() != CodeGenOpt::None) {
168 if (!getARMSubtarget().isThumb1Only()) {
169 addPass(createARMLoadStoreOptimizationPass());
170 printAndVerify("After ARM load / store optimizer");
172 if (getARMSubtarget().hasNEON())
173 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
176 // Expand some pseudo instructions into multiple instructions to allow
177 // proper scheduling.
178 addPass(createARMExpandPseudoPass());
180 if (getOptLevel() != CodeGenOpt::None) {
181 if (!getARMSubtarget().isThumb1Only())
182 addPass(&IfConverterID);
184 if (getARMSubtarget().isThumb2())
185 addPass(createThumb2ITBlockPass());
190 bool ARMPassConfig::addPreEmitPass() {
191 if (getARMSubtarget().isThumb2()) {
192 if (!getARMSubtarget().prefers32BitThumb())
193 addPass(createThumb2SizeReductionPass());
195 // Constant island pass work on unbundled instructions.
196 addPass(&UnpackMachineBundlesID);
199 addPass(createARMConstantIslandPass());
204 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
205 JITCodeEmitter &JCE) {
206 // Machine code emitter pass for ARM.
207 PM.add(createARMJITCodeEmitterPass(*this, JCE));