lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameLowering.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  26   Triple TheTriple(TT);
  27
  28   if (TheTriple.isOSDarwin())
  29     return new ARMMCAsmInfoDarwin();
  30
  31   return new ARMELFMCAsmInfo();
  32 }
  33
  34 // This is duplicated code. Refactor this.
  35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  36                                     MCContext &Ctx, TargetAsmBackend &TAB,
  37                                     raw_ostream &OS,
  38                                     MCCodeEmitter *Emitter,
  39                                     bool RelaxAll,
  40                                     bool NoExecStack) {
  41   Triple TheTriple(TT);
  42
  43   if (TheTriple.isOSDarwin())
  44     return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
  45
  46   if (TheTriple.isOSWindows()) {
  47     llvm_unreachable("ARM does not support Windows COFF format");
  48     return NULL;
  49   }
  50
  51   return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
  52 }
  53
  54 extern "C" void LLVMInitializeARMTarget() {
  55   // Register the target.
  56   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  57   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  58
  59   // Register the target asm info.
  60   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  61   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  62
  63   // Register the MC Code Emitter
  64   TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
  65   TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
  66
  67   // Register the asm backend.
  68   TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
  69   TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
  70
  71   // Register the object streamer.
  72   TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
  73   TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
  74
  75 }
  76
  77 /// TargetMachine ctor - Create an ARM architecture model.
  78 ///
  79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  80                                            const std::string &TT,
  81                                            const std::string &CPU,
  82                                            const std::string &FS,
  83                                            bool isThumb)
  84   : LLVMTargetMachine(T, TT),
  85     Subtarget(TT, CPU, FS, isThumb),
  86     JITInfo(),
  87     InstrItins(Subtarget.getInstrItineraryData()) {
  88   DefRelocModel = getRelocationModel();
  89
  90   // Default to soft float ABI
  91   if (FloatABIType == FloatABI::Default)
  92     FloatABIType = FloatABI::Soft;
  93 }
  94
  95 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  96                                    const std::string &CPU,
  97                                    const std::string &FS)
  98   : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget),
  99     DataLayout(Subtarget.isAPCS_ABI() ?
 100                std::string("e-p:32:32-f64:32:64-i64:32:64-"
 101                            "v128:32:128-v64:32:64-n32") :
 102                std::string("e-p:32:32-f64:64:64-i64:64:64-"
 103                            "v128:64:128-v64:64:64-n32")),
 104     ELFWriterInfo(*this),
 105     TLInfo(*this),
 106     TSInfo(*this),
 107     FrameLowering(Subtarget) {
 108   if (!Subtarget.hasARMOps())
 109     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 110                        "support ARM mode execution!");
 111 }
 112
 113 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 114                                        const std::string &CPU,
 115                                        const std::string &FS)
 116   : ARMBaseTargetMachine(T, TT, CPU, FS, true),
 117     InstrInfo(Subtarget.hasThumb2()
 118               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 119               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 120     DataLayout(Subtarget.isAPCS_ABI() ?
 121                std::string("e-p:32:32-f64:32:64-i64:32:64-"
 122                            "i16:16:32-i8:8:32-i1:8:32-"
 123                            "v128:32:128-v64:32:64-a:0:32-n32") :
 124                std::string("e-p:32:32-f64:64:64-i64:64:64-"
 125                            "i16:16:32-i8:8:32-i1:8:32-"
 126                            "v128:64:128-v64:64:64-a:0:32-n32")),
 127     ELFWriterInfo(*this),
 128     TLInfo(*this),
 129     TSInfo(*this),
 130     FrameLowering(Subtarget.hasThumb2()
 131               ? new ARMFrameLowering(Subtarget)
 132               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
 133 }
 134
 135 // Pass Pipeline Configuration
 136 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 137                                       CodeGenOpt::Level OptLevel) {
 138   if (OptLevel != CodeGenOpt::None)
 139     PM.add(createARMGlobalMergePass(getTargetLowering()));
 140
 141   return false;
 142 }
 143
 144 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 145                                            CodeGenOpt::Level OptLevel) {
 146   PM.add(createARMISelDag(*this, OptLevel));
 147   return false;
 148 }
 149
 150 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 151                                           CodeGenOpt::Level OptLevel) {
 152   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 153   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 154     PM.add(createARMLoadStoreOptimizationPass(true));
 155   if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
 156     PM.add(createMLxExpansionPass());
 157
 158   return true;
 159 }
 160
 161 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 162                                         CodeGenOpt::Level OptLevel) {
 163   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 164   if (OptLevel != CodeGenOpt::None) {
 165     if (!Subtarget.isThumb1Only())
 166       PM.add(createARMLoadStoreOptimizationPass());
 167     if (Subtarget.hasNEON())
 168       PM.add(createNEONMoveFixPass());
 169   }
 170
 171   // Expand some pseudo instructions into multiple instructions to allow
 172   // proper scheduling.
 173   PM.add(createARMExpandPseudoPass());
 174
 175   if (OptLevel != CodeGenOpt::None) {
 176     if (!Subtarget.isThumb1Only())
 177       PM.add(createIfConverterPass());
 178   }
 179   if (Subtarget.isThumb2())
 180     PM.add(createThumb2ITBlockPass());
 181
 182   return true;
 183 }
 184
 185 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 186                                           CodeGenOpt::Level OptLevel) {
 187   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 188     PM.add(createThumb2SizeReductionPass());
 189
 190   PM.add(createARMConstantIslandPass());
 191   return true;
 192 }
 193
 194 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 195                                           CodeGenOpt::Level OptLevel,
 196                                           JITCodeEmitter &JCE) {
 197   // FIXME: Move this to TargetJITInfo!
 198   if (DefRelocModel == Reloc::Default)
 199     setRelocationModel(Reloc::Static);
 200
 201   // Machine code emitter pass for ARM.
 202   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 203   return false;
 204 }