lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMTargetAsmInfo.h"
  15 #include "ARMFrameInfo.h"
  16 #include "ARM.h"
  17 #include "llvm/Module.h"
  18 #include "llvm/PassManager.h"
  19 #include "llvm/CodeGen/Passes.h"
  20 #include "llvm/Support/CommandLine.h"
  21 #include "llvm/Support/FormattedStream.h"
  22 #include "llvm/Target/TargetMachineRegistry.h"
  23 #include "llvm/Target/TargetOptions.h"
  24 using namespace llvm;
  25
  26 static cl::opt<bool> DisableLdStOpti("disable-arm-loadstore-opti", cl::Hidden,
  27                               cl::desc("Disable load store optimization pass"));
  28 static cl::opt<bool> DisableIfConversion("disable-arm-if-conversion",cl::Hidden,
  29                               cl::desc("Disable if-conversion pass"));
  30
  31 /// ARMTargetMachineModule - Note that this is used on hosts that cannot link
  32 /// in a library unless there are references into the library.  In particular,
  33 /// it seems that it is not possible to get things to work on Win32 without
  34 /// this.  Though it is unused, do not remove it.
  35 extern "C" int ARMTargetMachineModule;
  36 int ARMTargetMachineModule = 0;
  37
  38 // Register the target.
  39 extern Target TheARMTarget;
  40 static RegisterTarget<ARMTargetMachine>   X(TheARMTarget, "arm",   "ARM");
  41
  42 extern Target TheThumbTarget;
  43 static RegisterTarget<ThumbTargetMachine> Y(TheThumbTarget, "thumb", "Thumb");
  44
  45 // Force static initialization.
  46 extern "C" void LLVMInitializeARMTarget() { }
  47
  48 // No assembler printer by default
  49 ARMBaseTargetMachine::AsmPrinterCtorFn ARMBaseTargetMachine::AsmPrinterCtor = 0;
  50
  51 /// TargetMachine ctor - Create an ARM architecture model.
  52 ///
  53 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  54                                            const Module &M,
  55                                            const std::string &FS,
  56                                            bool isThumb)
  57   : LLVMTargetMachine(T),
  58     Subtarget(M, FS, isThumb),
  59     FrameInfo(Subtarget),
  60     JITInfo(),
  61     InstrItins(Subtarget.getInstrItineraryData()) {
  62   DefRelocModel = getRelocationModel();
  63 }
  64
  65 ARMTargetMachine::ARMTargetMachine(const Target &T, const Module &M,
  66                                    const std::string &FS)
  67   : ARMBaseTargetMachine(T, M, FS, false), InstrInfo(Subtarget),
  68     DataLayout(Subtarget.isAPCS_ABI() ?
  69                std::string("e-p:32:32-f64:32:32-i64:32:32") :
  70                std::string("e-p:32:32-f64:64:64-i64:64:64")),
  71     TLInfo(*this) {
  72 }
  73
  74 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const Module &M,
  75                                        const std::string &FS)
  76   : ARMBaseTargetMachine(T, M, FS, true),
  77     DataLayout(Subtarget.isAPCS_ABI() ?
  78                std::string("e-p:32:32-f64:32:32-i64:32:32-"
  79                            "i16:16:32-i8:8:32-i1:8:32-a:0:32") :
  80                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  81                            "i16:16:32-i8:8:32-i1:8:32-a:0:32")),
  82     TLInfo(*this) {
  83   // Create the approriate type of Thumb InstrInfo
  84   if (Subtarget.hasThumb2())
  85     InstrInfo = new Thumb2InstrInfo(Subtarget);
  86   else
  87     InstrInfo = new Thumb1InstrInfo(Subtarget);
  88 }
  89
  90
  91 const TargetAsmInfo *ARMBaseTargetMachine::createTargetAsmInfo() const {
  92   switch (Subtarget.TargetType) {
  93    case ARMSubtarget::isDarwin:
  94     return new ARMDarwinTargetAsmInfo(*this);
  95    case ARMSubtarget::isELF:
  96     return new ARMELFTargetAsmInfo(*this);
  97    default:
  98     return new ARMGenericTargetAsmInfo(*this);
  99   }
 100 }
 101
 102
 103 // Pass Pipeline Configuration
 104 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 105                                            CodeGenOpt::Level OptLevel) {
 106   PM.add(createARMISelDag(*this));
 107   return false;
 108 }
 109
 110 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 111                                           CodeGenOpt::Level OptLevel) {
 112   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
 113   if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
 114     PM.add(createARMLoadStoreOptimizationPass(true));
 115   return true;
 116 }
 117
 118 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 119                                           CodeGenOpt::Level OptLevel) {
 120   // FIXME: temporarily disabling load / store optimization pass for Thumb mode.
 121   if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
 122     PM.add(createARMLoadStoreOptimizationPass());
 123
 124   if (OptLevel != CodeGenOpt::None &&
 125       !DisableIfConversion && !Subtarget.isThumb())
 126     PM.add(createIfConverterPass());
 127
 128   if (Subtarget.isThumb2())
 129     PM.add(createThumb2ITBlockPass());
 130
 131   PM.add(createARMConstantIslandPass());
 132   return true;
 133 }
 134
 135 bool ARMBaseTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
 136                                               CodeGenOpt::Level OptLevel,
 137                                               bool Verbose,
 138                                               formatted_raw_ostream &Out) {
 139   // Output assembly language.
 140   assert(AsmPrinterCtor && "AsmPrinter was not linked in");
 141   if (AsmPrinterCtor)
 142     PM.add(AsmPrinterCtor(Out, *this, Verbose));
 143
 144   return false;
 145 }
 146
 147
 148 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 149                                           CodeGenOpt::Level OptLevel,
 150                                           bool DumpAsm,
 151                                           MachineCodeEmitter &MCE) {
 152   // FIXME: Move this to TargetJITInfo!
 153   if (DefRelocModel == Reloc::Default)
 154     setRelocationModel(Reloc::Static);
 155
 156   // Machine code emitter pass for ARM.
 157   PM.add(createARMCodeEmitterPass(*this, MCE));
 158   if (DumpAsm)
 159     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 160
 161   return false;
 162 }
 163
 164 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 165                                           CodeGenOpt::Level OptLevel,
 166                                           bool DumpAsm,
 167                                           JITCodeEmitter &JCE) {
 168   // FIXME: Move this to TargetJITInfo!
 169   if (DefRelocModel == Reloc::Default)
 170     setRelocationModel(Reloc::Static);
 171
 172   // Machine code emitter pass for ARM.
 173   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 174   if (DumpAsm)
 175     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 176
 177   return false;
 178 }
 179
 180 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 181                                           CodeGenOpt::Level OptLevel,
 182                                           bool DumpAsm,
 183                                           ObjectCodeEmitter &OCE) {
 184   // FIXME: Move this to TargetJITInfo!
 185   if (DefRelocModel == Reloc::Default)
 186     setRelocationModel(Reloc::Static);
 187
 188   // Machine code emitter pass for ARM.
 189   PM.add(createARMObjectCodeEmitterPass(*this, OCE));
 190   if (DumpAsm)
 191     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 192
 193   return false;
 194 }
 195
 196 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 197                                                 CodeGenOpt::Level OptLevel,
 198                                                 bool DumpAsm,
 199                                                 MachineCodeEmitter &MCE) {
 200   // Machine code emitter pass for ARM.
 201   PM.add(createARMCodeEmitterPass(*this, MCE));
 202   if (DumpAsm)
 203     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 204
 205   return false;
 206 }
 207
 208 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 209                                                 CodeGenOpt::Level OptLevel,
 210                                                 bool DumpAsm,
 211                                                 JITCodeEmitter &JCE) {
 212   // Machine code emitter pass for ARM.
 213   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 214   if (DumpAsm)
 215     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 216
 217   return false;
 218 }
 219
 220 bool ARMBaseTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
 221                                             CodeGenOpt::Level OptLevel,
 222                                             bool DumpAsm,
 223                                             ObjectCodeEmitter &OCE) {
 224   // Machine code emitter pass for ARM.
 225   PM.add(createARMObjectCodeEmitterPass(*this, OCE));
 226   if (DumpAsm)
 227     addAssemblyEmitter(PM, OptLevel, true, ferrs());
 228
 229   return false;
 230 }
 231