lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameLowering.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  26   Triple TheTriple(TT);
  27   switch (TheTriple.getOS()) {
  28   case Triple::Darwin:
  29     return new ARMMCAsmInfoDarwin();
  30   default:
  31     return new ARMELFMCAsmInfo();
  32   }
  33 }
  34
  35 // This is duplicated code. Refactor this.
  36 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  37                                     MCContext &Ctx, TargetAsmBackend &TAB,
  38                                     raw_ostream &OS,
  39                                     MCCodeEmitter *Emitter,
  40                                     bool RelaxAll,
  41                                     bool NoExecStack) {
  42   switch (Triple(TT).getOS()) {
  43   case Triple::Darwin:
  44     return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
  45   case Triple::MinGW32:
  46   case Triple::Cygwin:
  47   case Triple::Win32:
  48     llvm_unreachable("ARM does not support Windows COFF format");
  49     return NULL;
  50   default:
  51     return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
  52   }
  53 }
  54
  55 extern "C" void LLVMInitializeARMTarget() {
  56   // Register the target.
  57   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  58   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  59
  60   // Register the target asm info.
  61   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  62   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  63
  64   // Register the MC Code Emitter
  65   TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
  66   TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
  67
  68   // Register the asm backend.
  69   TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
  70   TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
  71
  72   // Register the object streamer.
  73   TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
  74   TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
  75
  76 }
  77
  78 /// TargetMachine ctor - Create an ARM architecture model.
  79 ///
  80 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  81                                            const std::string &TT,
  82                                            const std::string &FS,
  83                                            bool isThumb)
  84   : LLVMTargetMachine(T, TT),
  85     Subtarget(TT, FS, isThumb),
  86     JITInfo(),
  87     InstrItins(Subtarget.getInstrItineraryData()) {
  88   DefRelocModel = getRelocationModel();
  89 }
  90
  91 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  92                                    const std::string &FS)
  93   : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
  94     DataLayout(Subtarget.isAPCS_ABI() ?
  95                std::string("e-p:32:32-f64:32:64-i64:32:64-"
  96                            "v128:32:128-v64:32:64-n32") :
  97                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  98                            "v128:64:128-v64:64:64-n32")),
  99     ELFWriterInfo(*this),
 100     TLInfo(*this),
 101     TSInfo(*this),
 102     FrameLowering(Subtarget) {
 103   if (!Subtarget.hasARMOps())
 104     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 105                        "support ARM mode execution!");
 106 }
 107
 108 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 109                                        const std::string &FS)
 110   : ARMBaseTargetMachine(T, TT, FS, true),
 111     InstrInfo(Subtarget.hasThumb2()
 112               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 113               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 114     DataLayout(Subtarget.isAPCS_ABI() ?
 115                std::string("e-p:32:32-f64:32:64-i64:32:64-"
 116                            "i16:16:32-i8:8:32-i1:8:32-"
 117                            "v128:32:128-v64:32:64-a:0:32-n32") :
 118                std::string("e-p:32:32-f64:64:64-i64:64:64-"
 119                            "i16:16:32-i8:8:32-i1:8:32-"
 120                            "v128:64:128-v64:64:64-a:0:32-n32")),
 121     ELFWriterInfo(*this),
 122     TLInfo(*this),
 123     TSInfo(*this),
 124     FrameLowering(Subtarget.hasThumb2()
 125               ? new ARMFrameLowering(Subtarget)
 126               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
 127 }
 128
 129 // Pass Pipeline Configuration
 130 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 131                                       CodeGenOpt::Level OptLevel) {
 132   if (OptLevel != CodeGenOpt::None)
 133     PM.add(createARMGlobalMergePass(getTargetLowering()));
 134
 135   return false;
 136 }
 137
 138 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 139                                            CodeGenOpt::Level OptLevel) {
 140   PM.add(createARMISelDag(*this, OptLevel));
 141   return false;
 142 }
 143
 144 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 145                                           CodeGenOpt::Level OptLevel) {
 146   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 147   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 148     PM.add(createARMLoadStoreOptimizationPass(true));
 149   if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
 150     PM.add(createMLxExpansionPass());
 151
 152   return true;
 153 }
 154
 155 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 156                                         CodeGenOpt::Level OptLevel) {
 157   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 158   if (OptLevel != CodeGenOpt::None) {
 159     if (!Subtarget.isThumb1Only())
 160       PM.add(createARMLoadStoreOptimizationPass());
 161     if (Subtarget.hasNEON())
 162       PM.add(createNEONMoveFixPass());
 163   }
 164
 165   // Expand some pseudo instructions into multiple instructions to allow
 166   // proper scheduling.
 167   PM.add(createARMExpandPseudoPass());
 168
 169   if (OptLevel != CodeGenOpt::None) {
 170     if (!Subtarget.isThumb1Only())
 171       PM.add(createIfConverterPass());
 172   }
 173   if (Subtarget.isThumb2())
 174     PM.add(createThumb2ITBlockPass());
 175
 176   return true;
 177 }
 178
 179 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 180                                           CodeGenOpt::Level OptLevel) {
 181   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 182     PM.add(createThumb2SizeReductionPass());
 183
 184   PM.add(createARMConstantIslandPass());
 185   return true;
 186 }
 187
 188 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 189                                           CodeGenOpt::Level OptLevel,
 190                                           JITCodeEmitter &JCE) {
 191   // FIXME: Move this to TargetJITInfo!
 192   if (DefRelocModel == Reloc::Default)
 193     setRelocationModel(Reloc::Static);
 194
 195   // Machine code emitter pass for ARM.
 196   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 197   return false;
 198 }