lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameLowering.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Target/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  26   Triple TheTriple(TT);
  27
  28   if (TheTriple.isOSDarwin())
  29     return new ARMMCAsmInfoDarwin();
  30
  31   return new ARMELFMCAsmInfo();
  32 }
  33
  34 // This is duplicated code. Refactor this.
  35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  36                                     MCContext &Ctx, TargetAsmBackend &TAB,
  37                                     raw_ostream &OS,
  38                                     MCCodeEmitter *Emitter,
  39                                     bool RelaxAll,
  40                                     bool NoExecStack) {
  41   Triple TheTriple(TT);
  42
  43   if (TheTriple.isOSDarwin())
  44     return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
  45
  46   if (TheTriple.isOSWindows()) {
  47     llvm_unreachable("ARM does not support Windows COFF format");
  48     return NULL;
  49   }
  50
  51   return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
  52 }
  53
  54 extern "C" void LLVMInitializeARMTarget() {
  55   // Register the target.
  56   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  57   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  58
  59   // Register the target asm info.
  60   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  61   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  62
  63   // Register the MC Code Emitter
  64   TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
  65   TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
  66
  67   // Register the asm backend.
  68   TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
  69   TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
  70
  71   // Register the object streamer.
  72   TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
  73   TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
  74
  75 }
  76
  77 /// TargetMachine ctor - Create an ARM architecture model.
  78 ///
  79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  80                                            const std::string &TT,
  81                                            const std::string &FS,
  82                                            bool isThumb)
  83   : LLVMTargetMachine(T, TT),
  84     Subtarget(TT, FS, isThumb),
  85     JITInfo(),
  86     InstrItins(Subtarget.getInstrItineraryData()) {
  87   DefRelocModel = getRelocationModel();
  88 }
  89
  90 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  91                                    const std::string &FS)
  92   : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
  93     DataLayout(Subtarget.isAPCS_ABI() ?
  94                std::string("e-p:32:32-f64:32:64-i64:32:64-"
  95                            "v128:32:128-v64:32:64-n32") :
  96                std::string("e-p:32:32-f64:64:64-i64:64:64-"
  97                            "v128:64:128-v64:64:64-n32")),
  98     ELFWriterInfo(*this),
  99     TLInfo(*this),
 100     TSInfo(*this),
 101     FrameLowering(Subtarget) {
 102   if (!Subtarget.hasARMOps())
 103     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 104                        "support ARM mode execution!");
 105 }
 106
 107 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 108                                        const std::string &FS)
 109   : ARMBaseTargetMachine(T, TT, FS, true),
 110     InstrInfo(Subtarget.hasThumb2()
 111               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 112               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 113     DataLayout(Subtarget.isAPCS_ABI() ?
 114                std::string("e-p:32:32-f64:32:64-i64:32:64-"
 115                            "i16:16:32-i8:8:32-i1:8:32-"
 116                            "v128:32:128-v64:32:64-a:0:32-n32") :
 117                std::string("e-p:32:32-f64:64:64-i64:64:64-"
 118                            "i16:16:32-i8:8:32-i1:8:32-"
 119                            "v128:64:128-v64:64:64-a:0:32-n32")),
 120     ELFWriterInfo(*this),
 121     TLInfo(*this),
 122     TSInfo(*this),
 123     FrameLowering(Subtarget.hasThumb2()
 124               ? new ARMFrameLowering(Subtarget)
 125               : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
 126 }
 127
 128 // Pass Pipeline Configuration
 129 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 130                                       CodeGenOpt::Level OptLevel) {
 131   if (OptLevel != CodeGenOpt::None)
 132     PM.add(createARMGlobalMergePass(getTargetLowering()));
 133
 134   return false;
 135 }
 136
 137 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 138                                            CodeGenOpt::Level OptLevel) {
 139   PM.add(createARMISelDag(*this, OptLevel));
 140   return false;
 141 }
 142
 143 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 144                                           CodeGenOpt::Level OptLevel) {
 145   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 146   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 147     PM.add(createARMLoadStoreOptimizationPass(true));
 148   if (OptLevel != CodeGenOpt::None && Subtarget.isCortexA9())
 149     PM.add(createMLxExpansionPass());
 150
 151   return true;
 152 }
 153
 154 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 155                                         CodeGenOpt::Level OptLevel) {
 156   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 157   if (OptLevel != CodeGenOpt::None) {
 158     if (!Subtarget.isThumb1Only())
 159       PM.add(createARMLoadStoreOptimizationPass());
 160     if (Subtarget.hasNEON())
 161       PM.add(createNEONMoveFixPass());
 162   }
 163
 164   // Expand some pseudo instructions into multiple instructions to allow
 165   // proper scheduling.
 166   PM.add(createARMExpandPseudoPass());
 167
 168   if (OptLevel != CodeGenOpt::None) {
 169     if (!Subtarget.isThumb1Only())
 170       PM.add(createIfConverterPass());
 171   }
 172   if (Subtarget.isThumb2())
 173     PM.add(createThumb2ITBlockPass());
 174
 175   return true;
 176 }
 177
 178 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 179                                           CodeGenOpt::Level OptLevel) {
 180   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 181     PM.add(createThumb2SizeReductionPass());
 182
 183   PM.add(createARMConstantIslandPass());
 184   return true;
 185 }
 186
 187 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 188                                           CodeGenOpt::Level OptLevel,
 189                                           JITCodeEmitter &JCE) {
 190   // FIXME: Move this to TargetJITInfo!
 191   if (DefRelocModel == Reloc::Default)
 192     setRelocationModel(Reloc::Static);
 193
 194   // Machine code emitter pass for ARM.
 195   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 196   return false;
 197 }