lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameInfo.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/FormattedStream.h"
  20 #include "llvm/Target/TargetOptions.h"
  21 #include "llvm/Target/TargetRegistry.h"
  22 using namespace llvm;
  23
  24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  25   Triple TheTriple(TT);
  26   switch (TheTriple.getOS()) {
  27   case Triple::Darwin:
  28     return new ARMMCAsmInfoDarwin();
  29   default:
  30     return new ARMELFMCAsmInfo();
  31   }
  32 }
  33
  34 // This is duplicated code. Refactor this.
  35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  36                                     MCContext &Ctx, TargetAsmBackend &TAB,
  37                                     raw_ostream &_OS,
  38                                     MCCodeEmitter *_Emitter,
  39                                     bool RelaxAll) {
  40   Triple TheTriple(TT);
  41   switch (TheTriple.getOS()) {
  42   case Triple::Darwin:
  43     return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
  44   case Triple::MinGW32:
  45   case Triple::MinGW64:
  46   case Triple::Cygwin:
  47   case Triple::Win32:
  48     llvm_unreachable("ARM does not support Windows COFF format");
  49     return NULL;
  50   default:
  51     return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
  52   }
  53 }
  54
  55 extern "C" void LLVMInitializeARMTarget() {
  56   // Register the target.
  57   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  58   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  59
  60   // Register the target asm info.
  61   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  62   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  63
  64   // Register the MC Code Emitter
  65   TargetRegistry::RegisterCodeEmitter(TheARMTarget,
  66                                       createARMMCCodeEmitter);
  67   TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
  68                                       createARMMCCodeEmitter);
  69
  70   // Register the object streamer.
  71   TargetRegistry::RegisterObjectStreamer(TheARMTarget,
  72                                          createMCStreamer);
  73   TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
  74                                          createMCStreamer);
  75
  76 }
  77
  78 /// TargetMachine ctor - Create an ARM architecture model.
  79 ///
  80 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  81                                            const std::string &TT,
  82                                            const std::string &FS,
  83                                            bool isThumb)
  84   : LLVMTargetMachine(T, TT),
  85     Subtarget(TT, FS, isThumb),
  86     FrameInfo(Subtarget),
  87     JITInfo(),
  88     InstrItins(Subtarget.getInstrItineraryData()),
  89     DataLayout(Subtarget.getDataLayout()),
  90     ELFWriterInfo(*this)
  91 {
  92   DefRelocModel = getRelocationModel();
  93 }
  94
  95 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  96                                    const std::string &FS)
  97   : ARMBaseTargetMachine(T, TT, FS, false),
  98     InstrInfo(Subtarget),
  99     TLInfo(*this),
 100     TSInfo(*this) {
 101   if (!Subtarget.hasARMOps())
 102     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 103                        "support ARM mode execution!");
 104 }
 105
 106 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 107                                        const std::string &FS)
 108   : ARMBaseTargetMachine(T, TT, FS, true),
 109     InstrInfo(Subtarget.hasThumb2()
 110               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 111               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 112     TLInfo(*this),
 113     TSInfo(*this) {
 114 }
 115
 116 // Pass Pipeline Configuration
 117 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 118                                       CodeGenOpt::Level OptLevel) {
 119   if (OptLevel != CodeGenOpt::None)
 120     PM.add(createARMGlobalMergePass(getTargetLowering()));
 121
 122   return false;
 123 }
 124
 125 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 126                                            CodeGenOpt::Level OptLevel) {
 127   PM.add(createARMISelDag(*this, OptLevel));
 128   return false;
 129 }
 130
 131 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 132                                           CodeGenOpt::Level OptLevel) {
 133   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 134   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 135     PM.add(createARMLoadStoreOptimizationPass(true));
 136
 137   return true;
 138 }
 139
 140 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 141                                         CodeGenOpt::Level OptLevel) {
 142   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 143   if (OptLevel != CodeGenOpt::None) {
 144     if (!Subtarget.isThumb1Only())
 145       PM.add(createARMLoadStoreOptimizationPass());
 146     if (Subtarget.hasNEON())
 147       PM.add(createNEONMoveFixPass());
 148   }
 149
 150   // Expand some pseudo instructions into multiple instructions to allow
 151   // proper scheduling.
 152   PM.add(createARMExpandPseudoPass());
 153
 154   if (OptLevel != CodeGenOpt::None) {
 155     if (!Subtarget.isThumb1Only())
 156       PM.add(createIfConverterPass());
 157   }
 158   if (Subtarget.isThumb2())
 159     PM.add(createThumb2ITBlockPass());
 160
 161   return true;
 162 }
 163
 164 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 165                                           CodeGenOpt::Level OptLevel) {
 166   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 167     PM.add(createThumb2SizeReductionPass());
 168
 169   PM.add(createARMConstantIslandPass());
 170   return true;
 171 }
 172
 173 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 174                                           CodeGenOpt::Level OptLevel,
 175                                           JITCodeEmitter &JCE) {
 176   // FIXME: Move this to TargetJITInfo!
 177   if (DefRelocModel == Reloc::Default)
 178     setRelocationModel(Reloc::Static);
 179
 180   // Machine code emitter pass for ARM.
 181   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 182   return false;
 183 }