1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
28 cl::desc("Inhibit optimization of S->D register accesses on A15"),
31 extern "C" void LLVMInitializeARMTarget() {
32 // Register the target.
33 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
34 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
38 /// TargetMachine ctor - Create an ARM architecture model.
40 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
46 Subtarget(TT, CPU, FS, Options),
48 InstrItins(Subtarget.getInstrItineraryData()) {
50 // Default to triple-appropriate float ABI
51 if (Options.FloatABIType == FloatABI::Default)
52 this->Options.FloatABIType =
53 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft;
56 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
57 // Add first the target-independent BasicTTI pass, then our ARM pass. This
58 // allows the ARM pass to delegate to the target independent layer when
60 PM.add(createBasicTargetTransformInfoPass(this));
61 PM.add(createARMTargetTransformInfoPass(this));
65 void ARMTargetMachine::anchor() { }
67 static std::string computeDataLayout(ARMSubtarget &ST) {
69 std::string Ret = "e";
71 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
73 // Pointers are 32 bits and aligned to 32 bits.
76 // On thumb, i16,i18 and i1 have natural aligment requirements, but we try to
79 Ret += "-i1:8:32-i8:8:32-i16:16:32";
81 // ABIs other than APC have 64 bit integers with natural alignment.
85 // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
86 // bits, others to 64 bits. We always try to align to 64 bits.
90 // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
91 // to 64. We always ty to give them natural alignment.
93 Ret += "-v64:32:64-v128:32:128";
95 Ret += "-v128:64:128";
97 // On thumb and APCS, only try to align aggregates to 32 bits (the default is
99 if (ST.isThumb() || ST.isAPCS_ABI())
102 // Integer registers are 32 bits.
105 // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
106 // aligned everywhere else.
107 if (ST.isTargetNaCl())
109 else if (ST.isAAPCS_ABI())
117 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
118 StringRef CPU, StringRef FS,
119 const TargetOptions &Options,
120 Reloc::Model RM, CodeModel::Model CM,
121 CodeGenOpt::Level OL)
122 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
123 InstrInfo(Subtarget),
124 DL(computeDataLayout(Subtarget)),
127 FrameLowering(Subtarget) {
129 if (!Subtarget.hasARMOps())
130 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
131 "support ARM mode execution!");
134 void ThumbTargetMachine::anchor() { }
136 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
137 StringRef CPU, StringRef FS,
138 const TargetOptions &Options,
139 Reloc::Model RM, CodeModel::Model CM,
140 CodeGenOpt::Level OL)
141 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
142 InstrInfo(Subtarget.hasThumb2()
143 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
144 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
145 DL(computeDataLayout(Subtarget)),
148 FrameLowering(Subtarget.hasThumb2()
149 ? new ARMFrameLowering(Subtarget)
150 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
155 /// ARM Code Generator Pass Configuration Options.
156 class ARMPassConfig : public TargetPassConfig {
158 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
159 : TargetPassConfig(TM, PM) {}
161 ARMBaseTargetMachine &getARMTargetMachine() const {
162 return getTM<ARMBaseTargetMachine>();
165 const ARMSubtarget &getARMSubtarget() const {
166 return *getARMTargetMachine().getSubtargetImpl();
169 bool addPreISel() override;
170 bool addInstSelector() override;
171 bool addPreRegAlloc() override;
172 bool addPreSched2() override;
173 bool addPreEmitPass() override;
177 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
178 return new ARMPassConfig(this, PM);
181 bool ARMPassConfig::addPreISel() {
182 if (TM->getOptLevel() != CodeGenOpt::None)
183 addPass(createGlobalMergePass(TM));
188 bool ARMPassConfig::addInstSelector() {
189 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
191 const ARMSubtarget *Subtarget = &getARMSubtarget();
192 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
193 TM->Options.EnableFastISel)
194 addPass(createARMGlobalBaseRegPass());
198 bool ARMPassConfig::addPreRegAlloc() {
199 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
200 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
201 addPass(createARMLoadStoreOptimizationPass(true));
202 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
203 addPass(createMLxExpansionPass());
204 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
205 // enabled when NEON is available.
206 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
207 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
208 addPass(createA15SDOptimizerPass());
213 bool ARMPassConfig::addPreSched2() {
214 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
215 if (getOptLevel() != CodeGenOpt::None) {
216 if (!getARMSubtarget().isThumb1Only()) {
217 addPass(createARMLoadStoreOptimizationPass());
218 printAndVerify("After ARM load / store optimizer");
220 if (getARMSubtarget().hasNEON())
221 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
224 // Expand some pseudo instructions into multiple instructions to allow
225 // proper scheduling.
226 addPass(createARMExpandPseudoPass());
228 if (getOptLevel() != CodeGenOpt::None) {
229 if (!getARMSubtarget().isThumb1Only()) {
230 // in v8, IfConversion depends on Thumb instruction widths
231 if (getARMSubtarget().restrictIT() &&
232 !getARMSubtarget().prefers32BitThumb())
233 addPass(createThumb2SizeReductionPass());
234 addPass(&IfConverterID);
237 if (getARMSubtarget().isThumb2())
238 addPass(createThumb2ITBlockPass());
243 bool ARMPassConfig::addPreEmitPass() {
244 if (getARMSubtarget().isThumb2()) {
245 if (!getARMSubtarget().prefers32BitThumb())
246 addPass(createThumb2SizeReductionPass());
248 // Constant island pass work on unbundled instructions.
249 addPass(&UnpackMachineBundlesID);
252 addPass(createARMConstantIslandPass());
257 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
258 JITCodeEmitter &JCE) {
259 // Machine code emitter pass for ARM.
260 PM.add(createARMJITCodeEmitterPass(*this, JCE));