1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
15 #include "ARMFrameLowering.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/Transforms/Scalar.h"
27 EnableGlobalMerge("global-merge", cl::Hidden,
28 cl::desc("Enable global merge pass"),
32 DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
33 cl::desc("Inhibit optimization of S->D register accesses on A15"),
36 extern "C" void LLVMInitializeARMTarget() {
37 // Register the target.
38 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
39 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
43 /// TargetMachine ctor - Create an ARM architecture model.
45 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
46 StringRef CPU, StringRef FS,
47 const TargetOptions &Options,
48 Reloc::Model RM, CodeModel::Model CM,
50 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
51 Subtarget(TT, CPU, FS, Options),
53 InstrItins(Subtarget.getInstrItineraryData()) {
54 // Default to soft float ABI
55 if (Options.FloatABIType == FloatABI::Default)
56 this->Options.FloatABIType = FloatABI::Soft;
59 void ARMBaseTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
60 // Add first the target-independent BasicTTI pass, then our ARM pass. This
61 // allows the ARM pass to delegate to the target independent layer when
63 PM.add(createBasicTargetTransformInfoPass(this));
64 PM.add(createARMTargetTransformInfoPass(this));
68 void ARMTargetMachine::anchor() { }
70 static std::string computeDataLayout(ARMSubtarget &ST) {
71 std::string Ret = "e-p:32:32";
74 Ret += "-f64:32:64-i64:32:64";
76 Ret += "-f64:64:64-i64:64:64";
79 Ret += "-i16:16:32-i8:8:32-i1:8:32";
82 Ret += "-v128:32:128-v64:32:64";
84 Ret += "-v128:64:128-v64:64:64";
99 ARMTargetMachine::ARMTargetMachine(const Target &T, StringRef TT,
100 StringRef CPU, StringRef FS,
101 const TargetOptions &Options,
102 Reloc::Model RM, CodeModel::Model CM,
103 CodeGenOpt::Level OL)
104 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
105 InstrInfo(Subtarget),
106 DL(computeDataLayout(Subtarget)),
109 FrameLowering(Subtarget) {
111 if (!Subtarget.hasARMOps())
112 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
113 "support ARM mode execution!");
116 void ThumbTargetMachine::anchor() { }
118 ThumbTargetMachine::ThumbTargetMachine(const Target &T, StringRef TT,
119 StringRef CPU, StringRef FS,
120 const TargetOptions &Options,
121 Reloc::Model RM, CodeModel::Model CM,
122 CodeGenOpt::Level OL)
123 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
124 InstrInfo(Subtarget.hasThumb2()
125 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
126 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
127 DL(computeDataLayout(Subtarget)),
130 FrameLowering(Subtarget.hasThumb2()
131 ? new ARMFrameLowering(Subtarget)
132 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
137 /// ARM Code Generator Pass Configuration Options.
138 class ARMPassConfig : public TargetPassConfig {
140 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
141 : TargetPassConfig(TM, PM) {}
143 ARMBaseTargetMachine &getARMTargetMachine() const {
144 return getTM<ARMBaseTargetMachine>();
147 const ARMSubtarget &getARMSubtarget() const {
148 return *getARMTargetMachine().getSubtargetImpl();
151 virtual bool addPreISel();
152 virtual bool addInstSelector();
153 virtual bool addPreRegAlloc();
154 virtual bool addPreSched2();
155 virtual bool addPreEmitPass();
159 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
160 return new ARMPassConfig(this, PM);
163 bool ARMPassConfig::addPreISel() {
164 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
165 addPass(createGlobalMergePass(TM));
170 bool ARMPassConfig::addInstSelector() {
171 addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
173 const ARMSubtarget *Subtarget = &getARMSubtarget();
174 if (Subtarget->isTargetELF() && !Subtarget->isThumb1Only() &&
175 TM->Options.EnableFastISel)
176 addPass(createARMGlobalBaseRegPass());
180 bool ARMPassConfig::addPreRegAlloc() {
181 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
182 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
183 addPass(createARMLoadStoreOptimizationPass(true));
184 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
185 addPass(createMLxExpansionPass());
186 // Since the A15SDOptimizer pass can insert VDUP instructions, it can only be
187 // enabled when NEON is available.
188 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15() &&
189 getARMSubtarget().hasNEON() && !DisableA15SDOptimization) {
190 addPass(createA15SDOptimizerPass());
195 bool ARMPassConfig::addPreSched2() {
196 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
197 if (getOptLevel() != CodeGenOpt::None) {
198 if (!getARMSubtarget().isThumb1Only()) {
199 addPass(createARMLoadStoreOptimizationPass());
200 printAndVerify("After ARM load / store optimizer");
202 if (getARMSubtarget().hasNEON())
203 addPass(createExecutionDependencyFixPass(&ARM::DPRRegClass));
206 // Expand some pseudo instructions into multiple instructions to allow
207 // proper scheduling.
208 addPass(createARMExpandPseudoPass());
210 if (getOptLevel() != CodeGenOpt::None) {
211 if (!getARMSubtarget().isThumb1Only()) {
212 // in v8, IfConversion depends on Thumb instruction widths
213 if (getARMSubtarget().restrictIT() &&
214 !getARMSubtarget().prefers32BitThumb())
215 addPass(createThumb2SizeReductionPass());
216 addPass(&IfConverterID);
219 if (getARMSubtarget().isThumb2())
220 addPass(createThumb2ITBlockPass());
225 bool ARMPassConfig::addPreEmitPass() {
226 if (getARMSubtarget().isThumb2()) {
227 if (!getARMSubtarget().prefers32BitThumb())
228 addPass(createThumb2SizeReductionPass());
230 // Constant island pass work on unbundled instructions.
231 addPass(&UnpackMachineBundlesID);
234 addPass(createARMConstantIslandPass());
239 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
240 JITCodeEmitter &JCE) {
241 // Machine code emitter pass for ARM.
242 PM.add(createARMJITCodeEmitterPass(*this, JCE));