1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "ARMTargetMachine.h"
14 #include "ARMMCAsmInfo.h"
15 #include "ARMFrameLowering.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/Passes.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetRegistry.h"
25 static cl::opt<bool>ExpandMLx("expand-fp-mlx", cl::init(false), cl::Hidden);
27 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
29 switch (TheTriple.getOS()) {
31 return new ARMMCAsmInfoDarwin();
33 return new ARMELFMCAsmInfo();
37 // This is duplicated code. Refactor this.
38 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
39 MCContext &Ctx, TargetAsmBackend &TAB,
41 MCCodeEmitter *Emitter,
44 switch (Triple(TT).getOS()) {
46 return createMachOStreamer(Ctx, TAB, OS, Emitter, RelaxAll);
50 llvm_unreachable("ARM does not support Windows COFF format");
53 return createELFStreamer(Ctx, TAB, OS, Emitter, RelaxAll, NoExecStack);
57 extern "C" void LLVMInitializeARMTarget() {
58 // Register the target.
59 RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
60 RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
62 // Register the target asm info.
63 RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
64 RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
66 // Register the MC Code Emitter
67 TargetRegistry::RegisterCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
68 TargetRegistry::RegisterCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
70 // Register the asm backend.
71 TargetRegistry::RegisterAsmBackend(TheARMTarget, createARMAsmBackend);
72 TargetRegistry::RegisterAsmBackend(TheThumbTarget, createARMAsmBackend);
74 // Register the object streamer.
75 TargetRegistry::RegisterObjectStreamer(TheARMTarget, createMCStreamer);
76 TargetRegistry::RegisterObjectStreamer(TheThumbTarget, createMCStreamer);
80 /// TargetMachine ctor - Create an ARM architecture model.
82 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
83 const std::string &TT,
84 const std::string &FS,
86 : LLVMTargetMachine(T, TT),
87 Subtarget(TT, FS, isThumb),
89 InstrItins(Subtarget.getInstrItineraryData()) {
90 DefRelocModel = getRelocationModel();
93 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
94 const std::string &FS)
95 : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget),
96 DataLayout(Subtarget.isAPCS_ABI() ?
97 std::string("e-p:32:32-f64:32:64-i64:32:64-"
98 "v128:32:128-v64:32:64-n32") :
99 std::string("e-p:32:32-f64:64:64-i64:64:64-"
100 "v128:64:128-v64:64:64-n32")),
101 ELFWriterInfo(*this),
104 FrameLowering(Subtarget) {
105 if (!Subtarget.hasARMOps())
106 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
107 "support ARM mode execution!");
110 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
111 const std::string &FS)
112 : ARMBaseTargetMachine(T, TT, FS, true),
113 InstrInfo(Subtarget.hasThumb2()
114 ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
115 : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
116 DataLayout(Subtarget.isAPCS_ABI() ?
117 std::string("e-p:32:32-f64:32:64-i64:32:64-"
118 "i16:16:32-i8:8:32-i1:8:32-"
119 "v128:32:128-v64:32:64-a:0:32-n32") :
120 std::string("e-p:32:32-f64:64:64-i64:64:64-"
121 "i16:16:32-i8:8:32-i1:8:32-"
122 "v128:64:128-v64:64:64-a:0:32-n32")),
123 ELFWriterInfo(*this),
126 FrameLowering(Subtarget.hasThumb2()
127 ? new ARMFrameLowering(Subtarget)
128 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
131 // Pass Pipeline Configuration
132 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
133 CodeGenOpt::Level OptLevel) {
134 if (OptLevel != CodeGenOpt::None)
135 PM.add(createARMGlobalMergePass(getTargetLowering()));
140 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
141 CodeGenOpt::Level OptLevel) {
142 PM.add(createARMISelDag(*this, OptLevel));
146 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
147 CodeGenOpt::Level OptLevel) {
148 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
149 if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
150 PM.add(createARMLoadStoreOptimizationPass(true));
152 OptLevel != CodeGenOpt::None && Subtarget.hasVFP2())
153 PM.add(createMLxExpansionPass());
158 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
159 CodeGenOpt::Level OptLevel) {
160 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
161 if (OptLevel != CodeGenOpt::None) {
162 if (!Subtarget.isThumb1Only())
163 PM.add(createARMLoadStoreOptimizationPass());
164 if (Subtarget.hasNEON())
165 PM.add(createNEONMoveFixPass());
168 // Expand some pseudo instructions into multiple instructions to allow
169 // proper scheduling.
170 PM.add(createARMExpandPseudoPass());
172 if (OptLevel != CodeGenOpt::None) {
173 if (!Subtarget.isThumb1Only())
174 PM.add(createIfConverterPass());
176 if (Subtarget.isThumb2())
177 PM.add(createThumb2ITBlockPass());
182 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
183 CodeGenOpt::Level OptLevel) {
184 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
185 PM.add(createThumb2SizeReductionPass());
187 PM.add(createARMConstantIslandPass());
191 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
192 CodeGenOpt::Level OptLevel,
193 JITCodeEmitter &JCE) {
194 // FIXME: Move this to TargetJITInfo!
195 if (DefRelocModel == Reloc::Default)
196 setRelocationModel(Reloc::Static);
198 // Machine code emitter pass for ARM.
199 PM.add(createARMJITCodeEmitterPass(*this, JCE));