lib/Target/ARM/ARMTargetMachine.cpp

   1 //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "ARMTargetMachine.h"
  14 #include "ARMMCAsmInfo.h"
  15 #include "ARMFrameInfo.h"
  16 #include "ARM.h"
  17 #include "llvm/PassManager.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/FormattedStream.h"
  20 #include "llvm/Target/TargetOptions.h"
  21 #include "llvm/Target/TargetRegistry.h"
  22 using namespace llvm;
  23
  24 static MCAsmInfo *createMCAsmInfo(const Target &T, StringRef TT) {
  25   Triple TheTriple(TT);
  26   switch (TheTriple.getOS()) {
  27   case Triple::Darwin:
  28     return new ARMMCAsmInfoDarwin();
  29   default:
  30     return new ARMELFMCAsmInfo();
  31   }
  32 }
  33
  34 // This is duplicated code. Refactor this.
  35 static MCStreamer *createMCStreamer(const Target &T, const std::string &TT,
  36                                     MCContext &Ctx, TargetAsmBackend &TAB,
  37                                     raw_ostream &_OS,
  38                                     MCCodeEmitter *_Emitter,
  39                                     bool RelaxAll) {
  40   Triple TheTriple(TT);
  41   switch (TheTriple.getOS()) {
  42   case Triple::Darwin:
  43     return createMachOStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
  44   case Triple::MinGW32:
  45   case Triple::MinGW64:
  46   case Triple::Cygwin:
  47   case Triple::Win32:
  48     assert(0 && "ARM does not support Windows COFF format"); break;
  49   default:
  50     return createELFStreamer(Ctx, TAB, _OS, _Emitter, RelaxAll);
  51   }
  52 }
  53
  54 extern "C" void LLVMInitializeARMTarget() {
  55   // Register the target.
  56   RegisterTargetMachine<ARMTargetMachine> X(TheARMTarget);
  57   RegisterTargetMachine<ThumbTargetMachine> Y(TheThumbTarget);
  58
  59   // Register the target asm info.
  60   RegisterAsmInfoFn A(TheARMTarget, createMCAsmInfo);
  61   RegisterAsmInfoFn B(TheThumbTarget, createMCAsmInfo);
  62
  63   // Register the MC Code Emitter
  64   TargetRegistry::RegisterCodeEmitter(TheARMTarget,
  65                                       createARMMCCodeEmitter);
  66   TargetRegistry::RegisterCodeEmitter(TheThumbTarget,
  67                                       createARMMCCodeEmitter);
  68
  69   // Register the object streamer.
  70   TargetRegistry::RegisterObjectStreamer(TheARMTarget,
  71                                          createMCStreamer);
  72   TargetRegistry::RegisterObjectStreamer(TheThumbTarget,
  73                                          createMCStreamer);
  74
  75 }
  76
  77 /// TargetMachine ctor - Create an ARM architecture model.
  78 ///
  79 ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T,
  80                                            const std::string &TT,
  81                                            const std::string &FS,
  82                                            bool isThumb)
  83   : LLVMTargetMachine(T, TT),
  84     Subtarget(TT, FS, isThumb),
  85     FrameInfo(Subtarget),
  86     JITInfo(),
  87     InstrItins(Subtarget.getInstrItineraryData()),
  88     DataLayout(Subtarget.getDataLayout()),
  89     ELFWriterInfo(*this)
  90 {
  91   DefRelocModel = getRelocationModel();
  92 }
  93
  94 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,
  95                                    const std::string &FS)
  96   : ARMBaseTargetMachine(T, TT, FS, false),
  97     InstrInfo(Subtarget),
  98     TLInfo(*this),
  99     TSInfo(*this) {
 100   if (!Subtarget.hasARMOps())
 101     report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not "
 102                        "support ARM mode execution!");
 103 }
 104
 105 ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT,
 106                                        const std::string &FS)
 107   : ARMBaseTargetMachine(T, TT, FS, true),
 108     InstrInfo(Subtarget.hasThumb2()
 109               ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget))
 110               : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))),
 111     TLInfo(*this),
 112     TSInfo(*this) {
 113 }
 114
 115 // Pass Pipeline Configuration
 116 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM,
 117                                       CodeGenOpt::Level OptLevel) {
 118   if (OptLevel != CodeGenOpt::None)
 119     PM.add(createARMGlobalMergePass(getTargetLowering()));
 120
 121   return false;
 122 }
 123
 124 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM,
 125                                            CodeGenOpt::Level OptLevel) {
 126   PM.add(createARMISelDag(*this, OptLevel));
 127   return false;
 128 }
 129
 130 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
 131                                           CodeGenOpt::Level OptLevel) {
 132   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 133   if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
 134     PM.add(createARMLoadStoreOptimizationPass(true));
 135
 136   return true;
 137 }
 138
 139 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
 140                                         CodeGenOpt::Level OptLevel) {
 141   // FIXME: temporarily disabling load / store optimization pass for Thumb1.
 142   if (OptLevel != CodeGenOpt::None) {
 143     if (!Subtarget.isThumb1Only())
 144       PM.add(createARMLoadStoreOptimizationPass());
 145     if (Subtarget.hasNEON())
 146       PM.add(createNEONMoveFixPass());
 147   }
 148
 149   // Expand some pseudo instructions into multiple instructions to allow
 150   // proper scheduling.
 151   PM.add(createARMExpandPseudoPass());
 152
 153   if (OptLevel != CodeGenOpt::None) {
 154     if (!Subtarget.isThumb1Only())
 155       PM.add(createIfConverterPass());
 156   }
 157   if (Subtarget.isThumb2())
 158     PM.add(createThumb2ITBlockPass());
 159
 160   return true;
 161 }
 162
 163 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
 164                                           CodeGenOpt::Level OptLevel) {
 165   if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
 166     PM.add(createThumb2SizeReductionPass());
 167
 168   PM.add(createARMConstantIslandPass());
 169   return true;
 170 }
 171
 172 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
 173                                           CodeGenOpt::Level OptLevel,
 174                                           JITCodeEmitter &JCE) {
 175   // FIXME: Move this to TargetJITInfo!
 176   if (DefRelocModel == Reloc::Default)
 177     setRelocationModel(Reloc::Static);
 178
 179   // Machine code emitter pass for ARM.
 180   PM.add(createARMJITCodeEmitterPass(*this, JCE));
 181   return false;
 182 }