1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "ARMSelectionDAGInfo.h"
25 #include "Thumb1InstrInfo.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/ADT/OwningPtr.h"
31 class ARMBaseTargetMachine : public LLVMTargetMachine {
33 ARMSubtarget Subtarget;
36 ARMFrameInfo FrameInfo;
38 InstrItineraryData InstrItins;
39 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
42 ARMBaseTargetMachine(const Target &T, const std::string &TT,
43 const std::string &FS, bool isThumb);
45 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
46 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
47 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
48 virtual const InstrItineraryData getInstrItineraryData() const {
52 // Pass Pipeline Configuration
53 virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
58 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
62 /// ARMTargetMachine - ARM target machine.
64 class ARMTargetMachine : public ARMBaseTargetMachine {
65 ARMInstrInfo InstrInfo;
66 const TargetData DataLayout; // Calculates type size & alignment
67 ARMTargetLowering TLInfo;
68 ARMSelectionDAGInfo TSInfo;
70 ARMTargetMachine(const Target &T, const std::string &TT,
71 const std::string &FS);
73 virtual const ARMRegisterInfo *getRegisterInfo() const {
74 return &InstrInfo.getRegisterInfo();
77 virtual const ARMTargetLowering *getTargetLowering() const {
81 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
85 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
86 virtual const TargetData *getTargetData() const { return &DataLayout; }
89 /// ThumbTargetMachine - Thumb target machine.
90 /// Due to the way architectures are handled, this represents both
91 /// Thumb-1 and Thumb-2.
93 class ThumbTargetMachine : public ARMBaseTargetMachine {
94 // Either Thumb1InstrInfo or Thumb2InstrInfo.
95 OwningPtr<ARMBaseInstrInfo> InstrInfo;
96 const TargetData DataLayout; // Calculates type size & alignment
97 ARMTargetLowering TLInfo;
98 ARMSelectionDAGInfo TSInfo;
100 ThumbTargetMachine(const Target &T, const std::string &TT,
101 const std::string &FS);
103 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
104 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
105 return &InstrInfo->getRegisterInfo();
108 virtual const ARMTargetLowering *getTargetLowering() const {
112 virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
116 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
117 virtual const ARMBaseInstrInfo *getInstrInfo() const {
118 return InstrInfo.get();
120 virtual const TargetData *getTargetData() const { return &DataLayout; }
123 } // end namespace llvm