1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 ARMSubtarget Subtarget;
28 ARMBaseTargetMachine(const Target &T, StringRef TT,
29 StringRef CPU, StringRef FS,
30 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
35 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
37 /// \brief Register ARM analysis passes with a pass manager.
38 void addAnalysisPasses(PassManagerBase &PM) override;
40 // Pass Pipeline Configuration
41 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
44 /// ARMTargetMachine - ARM target machine.
46 class ARMTargetMachine : public ARMBaseTargetMachine {
47 virtual void anchor();
49 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
50 const TargetOptions &Options, Reloc::Model RM,
51 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
54 /// ARMLETargetMachine - ARM little endian target machine.
56 class ARMLETargetMachine : public ARMTargetMachine {
57 void anchor() override;
59 ARMLETargetMachine(const Target &T, StringRef TT,
60 StringRef CPU, StringRef FS, const TargetOptions &Options,
61 Reloc::Model RM, CodeModel::Model CM,
62 CodeGenOpt::Level OL);
65 /// ARMBETargetMachine - ARM big endian target machine.
67 class ARMBETargetMachine : public ARMTargetMachine {
68 void anchor() override;
70 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
71 const TargetOptions &Options, Reloc::Model RM,
72 CodeModel::Model CM, CodeGenOpt::Level OL);
75 /// ThumbTargetMachine - Thumb target machine.
76 /// Due to the way architectures are handled, this represents both
77 /// Thumb-1 and Thumb-2.
79 class ThumbTargetMachine : public ARMBaseTargetMachine {
80 virtual void anchor();
82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
83 const TargetOptions &Options, Reloc::Model RM,
84 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
87 /// ThumbLETargetMachine - Thumb little endian target machine.
89 class ThumbLETargetMachine : public ThumbTargetMachine {
90 void anchor() override;
92 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
93 StringRef FS, const TargetOptions &Options,
94 Reloc::Model RM, CodeModel::Model CM,
95 CodeGenOpt::Level OL);
98 /// ThumbBETargetMachine - Thumb big endian target machine.
100 class ThumbBETargetMachine : public ThumbTargetMachine {
101 void anchor() override;
103 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
104 StringRef FS, const TargetOptions &Options,
105 Reloc::Model RM, CodeModel::Model CM,
106 CodeGenOpt::Level OL);
109 } // end namespace llvm