1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS // ARM EABI
34 std::unique_ptr<TargetLoweringObjectFile> TLOF;
35 ARMSubtarget Subtarget;
37 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
40 ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
46 ~ARMBaseTargetMachine() override;
48 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
50 const DataLayout *getDataLayout() const override { return &DL; }
51 bool isLittleEndian() const { return isLittle; }
53 /// \brief Get the TargetIRAnalysis for this target.
54 TargetIRAnalysis getTargetIRAnalysis() override;
56 // Pass Pipeline Configuration
57 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
59 TargetLoweringObjectFile *getObjFileLowering() const override {
64 /// ARMTargetMachine - ARM target machine.
66 class ARMTargetMachine : public ARMBaseTargetMachine {
67 virtual void anchor();
69 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
70 const TargetOptions &Options, Reloc::Model RM,
71 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
74 /// ARMLETargetMachine - ARM little endian target machine.
76 class ARMLETargetMachine : public ARMTargetMachine {
77 void anchor() override;
79 ARMLETargetMachine(const Target &T, StringRef TT,
80 StringRef CPU, StringRef FS, const TargetOptions &Options,
81 Reloc::Model RM, CodeModel::Model CM,
82 CodeGenOpt::Level OL);
85 /// ARMBETargetMachine - ARM big endian target machine.
87 class ARMBETargetMachine : public ARMTargetMachine {
88 void anchor() override;
90 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
91 const TargetOptions &Options, Reloc::Model RM,
92 CodeModel::Model CM, CodeGenOpt::Level OL);
95 /// ThumbTargetMachine - Thumb target machine.
96 /// Due to the way architectures are handled, this represents both
97 /// Thumb-1 and Thumb-2.
99 class ThumbTargetMachine : public ARMBaseTargetMachine {
100 virtual void anchor();
102 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
103 const TargetOptions &Options, Reloc::Model RM,
104 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
107 /// ThumbLETargetMachine - Thumb little endian target machine.
109 class ThumbLETargetMachine : public ThumbTargetMachine {
110 void anchor() override;
112 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
113 StringRef FS, const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL);
118 /// ThumbBETargetMachine - Thumb big endian target machine.
120 class ThumbBETargetMachine : public ThumbTargetMachine {
121 void anchor() override;
123 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
124 StringRef FS, const TargetOptions &Options,
125 Reloc::Model RM, CodeModel::Model CM,
126 CodeGenOpt::Level OL);
129 } // end namespace llvm