1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
29 class ARMBaseTargetMachine : public LLVMTargetMachine {
31 ARMSubtarget Subtarget;
34 ARMFrameInfo FrameInfo;
36 InstrItineraryData InstrItins;
37 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
40 ARMBaseTargetMachine(const Target &T, const std::string &TT,
41 const std::string &FS, bool isThumb);
43 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
44 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
45 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
46 virtual const InstrItineraryData getInstrItineraryData() const {
50 // Pass Pipeline Configuration
51 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
52 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59 /// ARMTargetMachine - ARM target machine.
61 class ARMTargetMachine : public ARMBaseTargetMachine {
62 ARMInstrInfo InstrInfo;
63 const TargetData DataLayout; // Calculates type size & alignment
64 ARMTargetLowering TLInfo;
66 ARMTargetMachine(const Target &T, const std::string &TT,
67 const std::string &FS);
69 virtual const ARMRegisterInfo *getRegisterInfo() const {
70 return &InstrInfo.getRegisterInfo();
73 virtual ARMTargetLowering *getTargetLowering() const {
74 return const_cast<ARMTargetLowering*>(&TLInfo);
77 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
78 virtual const TargetData *getTargetData() const { return &DataLayout; }
81 /// ThumbTargetMachine - Thumb target machine.
82 /// Due to the way architectures are handled, this represents both
83 /// Thumb-1 and Thumb-2.
85 class ThumbTargetMachine : public ARMBaseTargetMachine {
86 ARMBaseInstrInfo *InstrInfo; // either Thumb1InstrInfo or Thumb2InstrInfo
87 const TargetData DataLayout; // Calculates type size & alignment
88 ARMTargetLowering TLInfo;
90 ThumbTargetMachine(const Target &T, const std::string &TT,
91 const std::string &FS);
93 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
94 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
95 return &InstrInfo->getRegisterInfo();
98 virtual ARMTargetLowering *getTargetLowering() const {
99 return const_cast<ARMTargetLowering*>(&TLInfo);
102 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
103 virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo; }
104 virtual const TargetData *getTargetData() const { return &DataLayout; }
107 } // end namespace llvm