1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS, // ARM EABI
34 std::unique_ptr<TargetLoweringObjectFile> TLOF;
35 ARMSubtarget Subtarget;
37 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
40 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
41 StringRef FS, const TargetOptions &Options,
42 Reloc::Model RM, CodeModel::Model CM,
43 CodeGenOpt::Level OL, bool isLittle);
44 ~ARMBaseTargetMachine() override;
46 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
47 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
48 bool isLittleEndian() const { return isLittle; }
50 /// \brief Get the TargetIRAnalysis for this target.
51 TargetIRAnalysis getTargetIRAnalysis() override;
53 // Pass Pipeline Configuration
54 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
56 TargetLoweringObjectFile *getObjFileLowering() const override {
61 /// ARMTargetMachine - ARM target machine.
63 class ARMTargetMachine : public ARMBaseTargetMachine {
64 virtual void anchor();
66 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
67 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
68 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
71 /// ARMLETargetMachine - ARM little endian target machine.
73 class ARMLETargetMachine : public ARMTargetMachine {
74 void anchor() override;
76 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
77 StringRef FS, const TargetOptions &Options,
78 Reloc::Model RM, CodeModel::Model CM,
79 CodeGenOpt::Level OL);
82 /// ARMBETargetMachine - ARM big endian target machine.
84 class ARMBETargetMachine : public ARMTargetMachine {
85 void anchor() override;
87 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
88 StringRef FS, const TargetOptions &Options,
89 Reloc::Model RM, CodeModel::Model CM,
90 CodeGenOpt::Level OL);
93 /// ThumbTargetMachine - Thumb target machine.
94 /// Due to the way architectures are handled, this represents both
95 /// Thumb-1 and Thumb-2.
97 class ThumbTargetMachine : public ARMBaseTargetMachine {
98 virtual void anchor();
100 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
101 StringRef FS, const TargetOptions &Options,
102 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
106 /// ThumbLETargetMachine - Thumb little endian target machine.
108 class ThumbLETargetMachine : public ThumbTargetMachine {
109 void anchor() override;
111 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
112 StringRef FS, const TargetOptions &Options,
113 Reloc::Model RM, CodeModel::Model CM,
114 CodeGenOpt::Level OL);
117 /// ThumbBETargetMachine - Thumb big endian target machine.
119 class ThumbBETargetMachine : public ThumbTargetMachine {
120 void anchor() override;
122 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
123 StringRef FS, const TargetOptions &Options,
124 Reloc::Model RM, CodeModel::Model CM,
125 CodeGenOpt::Level OL);
128 } // end namespace llvm