1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 ARMSubtarget Subtarget;
28 ARMBaseTargetMachine(const Target &T, StringRef TT,
29 StringRef CPU, StringRef FS,
30 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
35 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
37 /// \brief Register ARM analysis passes with a pass manager.
38 void addAnalysisPasses(PassManagerBase &PM) override;
40 // Pass Pipeline Configuration
41 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
43 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
46 /// ARMTargetMachine - ARM target machine.
48 class ARMTargetMachine : public ARMBaseTargetMachine {
49 virtual void anchor();
51 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
52 const TargetOptions &Options, Reloc::Model RM,
53 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
56 /// ARMLETargetMachine - ARM little endian target machine.
58 class ARMLETargetMachine : public ARMTargetMachine {
59 void anchor() override;
61 ARMLETargetMachine(const Target &T, StringRef TT,
62 StringRef CPU, StringRef FS, const TargetOptions &Options,
63 Reloc::Model RM, CodeModel::Model CM,
64 CodeGenOpt::Level OL);
67 /// ARMBETargetMachine - ARM big endian target machine.
69 class ARMBETargetMachine : public ARMTargetMachine {
70 void anchor() override;
72 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
73 const TargetOptions &Options, Reloc::Model RM,
74 CodeModel::Model CM, CodeGenOpt::Level OL);
77 /// ThumbTargetMachine - Thumb target machine.
78 /// Due to the way architectures are handled, this represents both
79 /// Thumb-1 and Thumb-2.
81 class ThumbTargetMachine : public ARMBaseTargetMachine {
82 virtual void anchor();
84 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 const TargetOptions &Options, Reloc::Model RM,
86 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
89 /// ThumbLETargetMachine - Thumb little endian target machine.
91 class ThumbLETargetMachine : public ThumbTargetMachine {
92 void anchor() override;
94 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
95 StringRef FS, const TargetOptions &Options,
96 Reloc::Model RM, CodeModel::Model CM,
97 CodeGenOpt::Level OL);
100 /// ThumbBETargetMachine - Thumb big endian target machine.
102 class ThumbBETargetMachine : public ThumbTargetMachine {
103 void anchor() override;
105 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
106 StringRef FS, const TargetOptions &Options,
107 Reloc::Model RM, CodeModel::Model CM,
108 CodeGenOpt::Level OL);
111 } // end namespace llvm