1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
29 ARM_ABI_AAPCS // ARM EABI
33 std::unique_ptr<TargetLoweringObjectFile> TLOF;
34 ARMSubtarget Subtarget;
36 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
39 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
40 StringRef FS, const TargetOptions &Options,
41 Reloc::Model RM, CodeModel::Model CM,
42 CodeGenOpt::Level OL, bool isLittle);
43 ~ARMBaseTargetMachine() override;
45 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
46 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
47 bool isLittleEndian() const { return isLittle; }
49 /// \brief Get the TargetIRAnalysis for this target.
50 TargetIRAnalysis getTargetIRAnalysis() override;
52 // Pass Pipeline Configuration
53 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
55 TargetLoweringObjectFile *getObjFileLowering() const override {
60 /// ARMTargetMachine - ARM target machine.
62 class ARMTargetMachine : public ARMBaseTargetMachine {
63 virtual void anchor();
65 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
66 StringRef FS, const TargetOptions &Options, Reloc::Model RM,
67 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
70 /// ARMLETargetMachine - ARM little endian target machine.
72 class ARMLETargetMachine : public ARMTargetMachine {
73 void anchor() override;
75 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
76 StringRef FS, const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
78 CodeGenOpt::Level OL);
81 /// ARMBETargetMachine - ARM big endian target machine.
83 class ARMBETargetMachine : public ARMTargetMachine {
84 void anchor() override;
86 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
87 StringRef FS, const TargetOptions &Options,
88 Reloc::Model RM, CodeModel::Model CM,
89 CodeGenOpt::Level OL);
92 /// ThumbTargetMachine - Thumb target machine.
93 /// Due to the way architectures are handled, this represents both
94 /// Thumb-1 and Thumb-2.
96 class ThumbTargetMachine : public ARMBaseTargetMachine {
97 virtual void anchor();
99 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
100 StringRef FS, const TargetOptions &Options,
101 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
105 /// ThumbLETargetMachine - Thumb little endian target machine.
107 class ThumbLETargetMachine : public ThumbTargetMachine {
108 void anchor() override;
110 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
111 StringRef FS, const TargetOptions &Options,
112 Reloc::Model RM, CodeModel::Model CM,
113 CodeGenOpt::Level OL);
116 /// ThumbBETargetMachine - Thumb big endian target machine.
118 class ThumbBETargetMachine : public ThumbTargetMachine {
119 void anchor() override;
121 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU,
122 StringRef FS, const TargetOptions &Options,
123 Reloc::Model RM, CodeModel::Model CM,
124 CodeGenOpt::Level OL);
127 } // end namespace llvm