1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/ADT/OwningPtr.h"
30 class ARMBaseTargetMachine : public LLVMTargetMachine {
32 ARMSubtarget Subtarget;
35 ARMFrameInfo FrameInfo;
37 InstrItineraryData InstrItins;
38 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
41 ARMBaseTargetMachine(const Target &T, const std::string &TT,
42 const std::string &FS, bool isThumb);
44 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
45 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
46 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
47 virtual const InstrItineraryData getInstrItineraryData() const {
51 // Pass Pipeline Configuration
52 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
60 /// ARMTargetMachine - ARM target machine.
62 class ARMTargetMachine : public ARMBaseTargetMachine {
63 ARMInstrInfo InstrInfo;
64 const TargetData DataLayout; // Calculates type size & alignment
65 ARMTargetLowering TLInfo;
67 ARMTargetMachine(const Target &T, const std::string &TT,
68 const std::string &FS);
70 virtual const ARMRegisterInfo *getRegisterInfo() const {
71 return &InstrInfo.getRegisterInfo();
74 virtual ARMTargetLowering *getTargetLowering() const {
75 return const_cast<ARMTargetLowering*>(&TLInfo);
78 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
79 virtual const TargetData *getTargetData() const { return &DataLayout; }
82 /// ThumbTargetMachine - Thumb target machine.
83 /// Due to the way architectures are handled, this represents both
84 /// Thumb-1 and Thumb-2.
86 class ThumbTargetMachine : public ARMBaseTargetMachine {
87 // Either Thumb1InstrInfo or Thumb2InstrInfo.
88 OwningPtr<ARMBaseInstrInfo> InstrInfo;
89 const TargetData DataLayout; // Calculates type size & alignment
90 ARMTargetLowering TLInfo;
92 ThumbTargetMachine(const Target &T, const std::string &TT,
93 const std::string &FS);
95 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
96 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
97 return &InstrInfo->getRegisterInfo();
100 virtual ARMTargetLowering *getTargetLowering() const {
101 return const_cast<ARMTargetLowering*>(&TLInfo);
104 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
105 virtual const ARMBaseInstrInfo *getInstrInfo() const {
106 return InstrInfo.get();
108 virtual const TargetData *getTargetData() const { return &DataLayout; }
111 } // end namespace llvm