1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMELFWriterInfo.h"
19 #include "ARMFrameLowering.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMISelLowering.h"
23 #include "ARMSelectionDAGInfo.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb1FrameLowering.h"
26 #include "Thumb2InstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/ADT/OwningPtr.h"
34 class ARMBaseTargetMachine : public LLVMTargetMachine {
36 ARMSubtarget Subtarget;
39 InstrItineraryData InstrItins;
42 ARMBaseTargetMachine(const Target &T, StringRef TT,
43 StringRef CPU, StringRef FS,
44 Reloc::Model RM, CodeModel::Model CM);
46 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
47 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
48 virtual const InstrItineraryData *getInstrItineraryData() const {
52 // Pass Pipeline Configuration
53 virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
58 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
62 /// ARMTargetMachine - ARM target machine.
64 class ARMTargetMachine : public ARMBaseTargetMachine {
65 ARMInstrInfo InstrInfo;
66 const TargetData DataLayout; // Calculates type size & alignment
67 ARMELFWriterInfo ELFWriterInfo;
68 ARMTargetLowering TLInfo;
69 ARMSelectionDAGInfo TSInfo;
70 ARMFrameLowering FrameLowering;
72 ARMTargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 Reloc::Model RM, CodeModel::Model CM);
76 virtual const ARMRegisterInfo *getRegisterInfo() const {
77 return &InstrInfo.getRegisterInfo();
80 virtual const ARMTargetLowering *getTargetLowering() const {
84 virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
87 virtual const ARMFrameLowering *getFrameLowering() const {
88 return &FrameLowering;
91 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
92 virtual const TargetData *getTargetData() const { return &DataLayout; }
93 virtual const ARMELFWriterInfo *getELFWriterInfo() const {
94 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
98 /// ThumbTargetMachine - Thumb target machine.
99 /// Due to the way architectures are handled, this represents both
100 /// Thumb-1 and Thumb-2.
102 class ThumbTargetMachine : public ARMBaseTargetMachine {
103 // Either Thumb1InstrInfo or Thumb2InstrInfo.
104 OwningPtr<ARMBaseInstrInfo> InstrInfo;
105 const TargetData DataLayout; // Calculates type size & alignment
106 ARMELFWriterInfo ELFWriterInfo;
107 ARMTargetLowering TLInfo;
108 ARMSelectionDAGInfo TSInfo;
109 // Either Thumb1FrameLowering or ARMFrameLowering.
110 OwningPtr<ARMFrameLowering> FrameLowering;
112 ThumbTargetMachine(const Target &T, StringRef TT,
113 StringRef CPU, StringRef FS,
114 Reloc::Model RM, CodeModel::Model CM);
116 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
117 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
118 return &InstrInfo->getRegisterInfo();
121 virtual const ARMTargetLowering *getTargetLowering() const {
125 virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
129 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
130 virtual const ARMBaseInstrInfo *getInstrInfo() const {
131 return InstrInfo.get();
133 /// returns either Thumb1FrameLowering or ARMFrameLowering
134 virtual const ARMFrameLowering *getFrameLowering() const {
135 return FrameLowering.get();
137 virtual const TargetData *getTargetData() const { return &DataLayout; }
138 virtual const ARMELFWriterInfo *getELFWriterInfo() const {
139 return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
143 } // end namespace llvm