1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetData.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMFrameInfo.h"
21 #include "ARMJITInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMISelLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
29 class ARMBaseTargetMachine : public LLVMTargetMachine {
31 ARMSubtarget Subtarget;
34 ARMFrameInfo FrameInfo;
36 InstrItineraryData InstrItins;
37 Reloc::Model DefRelocModel; // Reloc model before it's overridden.
40 ARMBaseTargetMachine(const Target &T, const std::string &TT,
41 const std::string &FS, bool isThumb);
43 virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; }
44 virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
45 virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
46 virtual const InstrItineraryData getInstrItineraryData() const {
50 // Pass Pipeline Configuration
51 virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
52 virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
53 virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54 virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
56 MachineCodeEmitter &MCE);
57 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59 virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
60 ObjectCodeEmitter &OCE);
61 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
62 CodeGenOpt::Level OptLevel,
63 MachineCodeEmitter &MCE);
64 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
65 CodeGenOpt::Level OptLevel,
67 virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
68 CodeGenOpt::Level OptLevel,
69 ObjectCodeEmitter &OCE);
72 /// ARMTargetMachine - ARM target machine.
74 class ARMTargetMachine : public ARMBaseTargetMachine {
75 ARMInstrInfo InstrInfo;
76 const TargetData DataLayout; // Calculates type size & alignment
77 ARMTargetLowering TLInfo;
79 ARMTargetMachine(const Target &T, const std::string &TT,
80 const std::string &FS);
82 virtual const ARMRegisterInfo *getRegisterInfo() const {
83 return &InstrInfo.getRegisterInfo();
86 virtual ARMTargetLowering *getTargetLowering() const {
87 return const_cast<ARMTargetLowering*>(&TLInfo);
90 virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
91 virtual const TargetData *getTargetData() const { return &DataLayout; }
94 /// ThumbTargetMachine - Thumb target machine.
95 /// Due to the way architectures are handled, this represents both
96 /// Thumb-1 and Thumb-2.
98 class ThumbTargetMachine : public ARMBaseTargetMachine {
99 ARMBaseInstrInfo *InstrInfo; // either Thumb1InstrInfo or Thumb2InstrInfo
100 const TargetData DataLayout; // Calculates type size & alignment
101 ARMTargetLowering TLInfo;
103 ThumbTargetMachine(const Target &T, const std::string &TT,
104 const std::string &FS);
106 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
107 virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
108 return &InstrInfo->getRegisterInfo();
111 virtual ARMTargetLowering *getTargetLowering() const {
112 return const_cast<ARMTargetLowering*>(&TLInfo);
115 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
116 virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo; }
117 virtual const TargetData *getTargetData() const { return &DataLayout; }
120 } // end namespace llvm