1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 std::unique_ptr<TargetLoweringObjectFile> TLOF;
27 ARMSubtarget Subtarget;
29 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
32 ARMBaseTargetMachine(const Target &T, StringRef TT,
33 StringRef CPU, StringRef FS,
34 const TargetOptions &Options,
35 Reloc::Model RM, CodeModel::Model CM,
39 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
40 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
42 /// \brief Register ARM analysis passes with a pass manager.
43 void addAnalysisPasses(PassManagerBase &PM) override;
45 // Pass Pipeline Configuration
46 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
48 TargetLoweringObjectFile *getObjFileLowering() const override {
53 /// ARMTargetMachine - ARM target machine.
55 class ARMTargetMachine : public ARMBaseTargetMachine {
56 virtual void anchor();
58 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
59 const TargetOptions &Options, Reloc::Model RM,
60 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
63 /// ARMLETargetMachine - ARM little endian target machine.
65 class ARMLETargetMachine : public ARMTargetMachine {
66 void anchor() override;
68 ARMLETargetMachine(const Target &T, StringRef TT,
69 StringRef CPU, StringRef FS, const TargetOptions &Options,
70 Reloc::Model RM, CodeModel::Model CM,
71 CodeGenOpt::Level OL);
74 /// ARMBETargetMachine - ARM big endian target machine.
76 class ARMBETargetMachine : public ARMTargetMachine {
77 void anchor() override;
79 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
80 const TargetOptions &Options, Reloc::Model RM,
81 CodeModel::Model CM, CodeGenOpt::Level OL);
84 /// ThumbTargetMachine - Thumb target machine.
85 /// Due to the way architectures are handled, this represents both
86 /// Thumb-1 and Thumb-2.
88 class ThumbTargetMachine : public ARMBaseTargetMachine {
89 virtual void anchor();
91 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
92 const TargetOptions &Options, Reloc::Model RM,
93 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
96 /// ThumbLETargetMachine - Thumb little endian target machine.
98 class ThumbLETargetMachine : public ThumbTargetMachine {
99 void anchor() override;
101 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
102 StringRef FS, const TargetOptions &Options,
103 Reloc::Model RM, CodeModel::Model CM,
104 CodeGenOpt::Level OL);
107 /// ThumbBETargetMachine - Thumb big endian target machine.
109 class ThumbBETargetMachine : public ThumbTargetMachine {
110 void anchor() override;
112 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
113 StringRef FS, const TargetOptions &Options,
114 Reloc::Model RM, CodeModel::Model CM,
115 CodeGenOpt::Level OL);
118 } // end namespace llvm