1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 ARMSubtarget Subtarget;
28 ARMBaseTargetMachine(const Target &T, StringRef TT,
29 StringRef CPU, StringRef FS,
30 const TargetOptions &Options,
31 Reloc::Model RM, CodeModel::Model CM,
35 using LLVMTargetMachine::getSubtargetImpl;
36 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
38 /// \brief Register ARM analysis passes with a pass manager.
39 void addAnalysisPasses(PassManagerBase &PM) override;
41 // Pass Pipeline Configuration
42 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
45 /// ARMTargetMachine - ARM target machine.
47 class ARMTargetMachine : public ARMBaseTargetMachine {
48 virtual void anchor();
50 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
51 const TargetOptions &Options, Reloc::Model RM,
52 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
55 /// ARMLETargetMachine - ARM little endian target machine.
57 class ARMLETargetMachine : public ARMTargetMachine {
58 void anchor() override;
60 ARMLETargetMachine(const Target &T, StringRef TT,
61 StringRef CPU, StringRef FS, const TargetOptions &Options,
62 Reloc::Model RM, CodeModel::Model CM,
63 CodeGenOpt::Level OL);
66 /// ARMBETargetMachine - ARM big endian target machine.
68 class ARMBETargetMachine : public ARMTargetMachine {
69 void anchor() override;
71 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
72 const TargetOptions &Options, Reloc::Model RM,
73 CodeModel::Model CM, CodeGenOpt::Level OL);
76 /// ThumbTargetMachine - Thumb target machine.
77 /// Due to the way architectures are handled, this represents both
78 /// Thumb-1 and Thumb-2.
80 class ThumbTargetMachine : public ARMBaseTargetMachine {
81 virtual void anchor();
83 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
84 const TargetOptions &Options, Reloc::Model RM,
85 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
88 /// ThumbLETargetMachine - Thumb little endian target machine.
90 class ThumbLETargetMachine : public ThumbTargetMachine {
91 void anchor() override;
93 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
94 StringRef FS, const TargetOptions &Options,
95 Reloc::Model RM, CodeModel::Model CM,
96 CodeGenOpt::Level OL);
99 /// ThumbBETargetMachine - Thumb big endian target machine.
101 class ThumbBETargetMachine : public ThumbTargetMachine {
102 void anchor() override;
104 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
105 StringRef FS, const TargetOptions &Options,
106 Reloc::Model RM, CodeModel::Model CM,
107 CodeGenOpt::Level OL);
110 } // end namespace llvm