1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H
17 #include "ARMInstrInfo.h"
18 #include "ARMSubtarget.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/Target/TargetMachine.h"
24 class ARMBaseTargetMachine : public LLVMTargetMachine {
26 std::unique_ptr<TargetLoweringObjectFile> TLOF;
27 ARMSubtarget Subtarget;
29 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
32 ARMBaseTargetMachine(const Target &T, StringRef TT,
33 StringRef CPU, StringRef FS,
34 const TargetOptions &Options,
35 Reloc::Model RM, CodeModel::Model CM,
38 ~ARMBaseTargetMachine() override;
40 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
41 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
43 /// \brief Register ARM analysis passes with a pass manager.
44 void addAnalysisPasses(PassManagerBase &PM) override;
46 // Pass Pipeline Configuration
47 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
49 TargetLoweringObjectFile *getObjFileLowering() const override {
54 /// ARMTargetMachine - ARM target machine.
56 class ARMTargetMachine : public ARMBaseTargetMachine {
57 virtual void anchor();
59 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
60 const TargetOptions &Options, Reloc::Model RM,
61 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
64 /// ARMLETargetMachine - ARM little endian target machine.
66 class ARMLETargetMachine : public ARMTargetMachine {
67 void anchor() override;
69 ARMLETargetMachine(const Target &T, StringRef TT,
70 StringRef CPU, StringRef FS, const TargetOptions &Options,
71 Reloc::Model RM, CodeModel::Model CM,
72 CodeGenOpt::Level OL);
75 /// ARMBETargetMachine - ARM big endian target machine.
77 class ARMBETargetMachine : public ARMTargetMachine {
78 void anchor() override;
80 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
81 const TargetOptions &Options, Reloc::Model RM,
82 CodeModel::Model CM, CodeGenOpt::Level OL);
85 /// ThumbTargetMachine - Thumb target machine.
86 /// Due to the way architectures are handled, this represents both
87 /// Thumb-1 and Thumb-2.
89 class ThumbTargetMachine : public ARMBaseTargetMachine {
90 virtual void anchor();
92 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 const TargetOptions &Options, Reloc::Model RM,
94 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
97 /// ThumbLETargetMachine - Thumb little endian target machine.
99 class ThumbLETargetMachine : public ThumbTargetMachine {
100 void anchor() override;
102 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
103 StringRef FS, const TargetOptions &Options,
104 Reloc::Model RM, CodeModel::Model CM,
105 CodeGenOpt::Level OL);
108 /// ThumbBETargetMachine - Thumb big endian target machine.
110 class ThumbBETargetMachine : public ThumbTargetMachine {
111 void anchor() override;
113 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
114 StringRef FS, const TargetOptions &Options,
115 Reloc::Model RM, CodeModel::Model CM,
116 CodeGenOpt::Level OL);
119 } // end namespace llvm