1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMTARGETMACHINE_H
15 #define ARMTARGETMACHINE_H
17 #include "ARMFrameLowering.h"
18 #include "ARMISelLowering.h"
19 #include "ARMInstrInfo.h"
20 #include "ARMJITInfo.h"
21 #include "ARMSelectionDAGInfo.h"
22 #include "ARMSubtarget.h"
23 #include "Thumb1FrameLowering.h"
24 #include "Thumb1InstrInfo.h"
25 #include "Thumb2InstrInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/MC/MCStreamer.h"
28 #include "llvm/Target/TargetMachine.h"
32 class ARMBaseTargetMachine : public LLVMTargetMachine {
34 ARMSubtarget Subtarget;
37 InstrItineraryData InstrItins;
40 ARMBaseTargetMachine(const Target &T, StringRef TT,
41 StringRef CPU, StringRef FS,
42 const TargetOptions &Options,
43 Reloc::Model RM, CodeModel::Model CM,
47 ARMJITInfo *getJITInfo() override { return &JITInfo; }
48 const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
49 const ARMTargetLowering *getTargetLowering() const override {
50 // Implemented by derived classes
51 llvm_unreachable("getTargetLowering not implemented");
53 const InstrItineraryData *getInstrItineraryData() const override {
57 /// \brief Register ARM analysis passes with a pass manager.
58 void addAnalysisPasses(PassManagerBase &PM) override;
60 // Pass Pipeline Configuration
61 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
63 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
66 /// ARMTargetMachine - ARM target machine.
68 class ARMTargetMachine : public ARMBaseTargetMachine {
69 virtual void anchor();
70 ARMInstrInfo InstrInfo;
71 ARMTargetLowering TLInfo;
72 ARMFrameLowering FrameLowering;
74 ARMTargetMachine(const Target &T, StringRef TT,
75 StringRef CPU, StringRef FS,
76 const TargetOptions &Options,
77 Reloc::Model RM, CodeModel::Model CM,
81 const ARMRegisterInfo *getRegisterInfo() const override {
82 return &InstrInfo.getRegisterInfo();
85 const ARMTargetLowering *getTargetLowering() const override {
89 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
90 return getSubtargetImpl()->getSelectionDAGInfo();
92 const ARMFrameLowering *getFrameLowering() const override {
93 return &FrameLowering;
95 const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
96 const DataLayout *getDataLayout() const override {
97 return getSubtargetImpl()->getDataLayout();
101 /// ARMLETargetMachine - ARM little endian target machine.
103 class ARMLETargetMachine : public ARMTargetMachine {
104 void anchor() override;
106 ARMLETargetMachine(const Target &T, StringRef TT,
107 StringRef CPU, StringRef FS, const TargetOptions &Options,
108 Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL);
112 /// ARMBETargetMachine - ARM big endian target machine.
114 class ARMBETargetMachine : public ARMTargetMachine {
115 void anchor() override;
117 ARMBETargetMachine(const Target &T, StringRef TT,
118 StringRef CPU, StringRef FS, const TargetOptions &Options,
119 Reloc::Model RM, CodeModel::Model CM,
120 CodeGenOpt::Level OL);
123 /// ThumbTargetMachine - Thumb target machine.
124 /// Due to the way architectures are handled, this represents both
125 /// Thumb-1 and Thumb-2.
127 class ThumbTargetMachine : public ARMBaseTargetMachine {
128 virtual void anchor();
129 // Either Thumb1InstrInfo or Thumb2InstrInfo.
130 std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
131 ARMTargetLowering TLInfo;
132 // Either Thumb1FrameLowering or ARMFrameLowering.
133 std::unique_ptr<ARMFrameLowering> FrameLowering;
135 ThumbTargetMachine(const Target &T, StringRef TT,
136 StringRef CPU, StringRef FS,
137 const TargetOptions &Options,
138 Reloc::Model RM, CodeModel::Model CM,
139 CodeGenOpt::Level OL,
142 /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
143 const ARMBaseRegisterInfo *getRegisterInfo() const override {
144 return &InstrInfo->getRegisterInfo();
147 const ARMTargetLowering *getTargetLowering() const override {
151 const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
152 return getSubtargetImpl()->getSelectionDAGInfo();
155 /// returns either Thumb1InstrInfo or Thumb2InstrInfo
156 const ARMBaseInstrInfo *getInstrInfo() const override {
157 return InstrInfo.get();
159 /// returns either Thumb1FrameLowering or ARMFrameLowering
160 const ARMFrameLowering *getFrameLowering() const override {
161 return FrameLowering.get();
163 const DataLayout *getDataLayout() const override {
164 return getSubtargetImpl()->getDataLayout();
168 /// ThumbLETargetMachine - Thumb little endian target machine.
170 class ThumbLETargetMachine : public ThumbTargetMachine {
171 void anchor() override;
173 ThumbLETargetMachine(const Target &T, StringRef TT,
174 StringRef CPU, StringRef FS, const TargetOptions &Options,
175 Reloc::Model RM, CodeModel::Model CM,
176 CodeGenOpt::Level OL);
179 /// ThumbBETargetMachine - Thumb big endian target machine.
181 class ThumbBETargetMachine : public ThumbTargetMachine {
182 void anchor() override;
184 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
185 StringRef FS, const TargetOptions &Options,
186 Reloc::Model RM, CodeModel::Model CM,
187 CodeGenOpt::Level OL);
190 } // end namespace llvm