1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "armtti"
19 #include "ARMTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeARMTTIPass(PassRegistry &);
35 class ARMTTI : public ImmutablePass, public TargetTransformInfo {
36 const ARMBaseTargetMachine *TM;
37 const ARMSubtarget *ST;
38 const ARMTargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 ARMTTI(const ARMBaseTargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeARMTTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
80 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
85 /// \name Vector TTI Implementations
88 unsigned getNumberOfRegisters(bool Vector) const {
95 if (ST->isThumb1Only())
100 unsigned getRegisterBitWidth(bool Vector) const {
110 unsigned getMaximumUnrollFactor() const {
111 // These are out of order CPUs:
112 if (ST->isCortexA15() || ST->isSwift())
117 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
118 int Index, Type *SubTp) const;
120 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
123 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
125 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
127 unsigned getAddressComputationCost(Type *Val) const;
131 } // end anonymous namespace
133 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
134 "ARM Target Transform Info", true, true, false)
138 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
139 return new ARMTTI(TM);
143 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
144 assert(Ty->isIntegerTy());
146 unsigned Bits = Ty->getPrimitiveSizeInBits();
147 if (Bits == 0 || Bits > 32)
150 int32_t SImmVal = Imm.getSExtValue();
151 uint32_t ZImmVal = Imm.getZExtValue();
152 if (!ST->isThumb()) {
153 if ((SImmVal >= 0 && SImmVal < 65536) ||
154 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
155 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
157 return ST->hasV6T2Ops() ? 2 : 3;
158 } else if (ST->isThumb2()) {
159 if ((SImmVal >= 0 && SImmVal < 65536) ||
160 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
161 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
163 return ST->hasV6T2Ops() ? 2 : 3;
165 if (SImmVal >= 0 && SImmVal < 256)
167 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
169 // Load from constantpool.
175 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
177 int ISD = TLI->InstructionOpcodeToISD(Opcode);
178 assert(ISD && "Invalid opcode");
180 EVT SrcTy = TLI->getValueType(Src);
181 EVT DstTy = TLI->getValueType(Dst);
183 if (!SrcTy.isSimple() || !DstTy.isSimple())
184 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
186 // Some arithmetic, load and store operations have specific instructions
187 // to cast up/down their types automatically at no extra cost.
188 // TODO: Get these tables to know at least what the related operations are.
189 static const TypeConversionCostTblEntry<MVT> NEONVectorConversionTbl[] = {
190 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
191 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
192 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
193 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
194 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
195 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
197 // Vector float <-> i32 conversions.
198 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
199 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
200 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
201 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
203 // Vector double <-> i32 conversions.
204 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
205 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
206 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
207 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }
210 if (SrcTy.isVector() && ST->hasNEON()) {
211 int Idx = ConvertCostTableLookup<MVT>(NEONVectorConversionTbl,
212 array_lengthof(NEONVectorConversionTbl),
213 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
215 return NEONVectorConversionTbl[Idx].Cost;
218 // Scalar float to integer conversions.
219 static const TypeConversionCostTblEntry<MVT> NEONFloatConversionTbl[] = {
220 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
221 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
222 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
223 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
224 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
225 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
226 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
227 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
228 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
229 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
230 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
231 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
232 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
233 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
234 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
235 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
236 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
237 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
238 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
239 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
241 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
242 int Idx = ConvertCostTableLookup<MVT>(NEONFloatConversionTbl,
243 array_lengthof(NEONFloatConversionTbl),
244 ISD, DstTy.getSimpleVT(),
245 SrcTy.getSimpleVT());
247 return NEONFloatConversionTbl[Idx].Cost;
251 // Scalar integer to float conversions.
252 static const TypeConversionCostTblEntry<MVT> NEONIntegerConversionTbl[] = {
253 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
254 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
255 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
256 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
257 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
258 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
259 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
260 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
261 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
262 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
263 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
264 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
265 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
266 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
267 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
268 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
269 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
270 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
271 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
272 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
275 if (SrcTy.isInteger() && ST->hasNEON()) {
276 int Idx = ConvertCostTableLookup<MVT>(NEONIntegerConversionTbl,
277 array_lengthof(NEONIntegerConversionTbl),
278 ISD, DstTy.getSimpleVT(),
279 SrcTy.getSimpleVT());
281 return NEONIntegerConversionTbl[Idx].Cost;
284 // Scalar integer conversion costs.
285 static const TypeConversionCostTblEntry<MVT> ARMIntegerConversionTbl[] = {
286 // i16 -> i64 requires two dependent operations.
287 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
289 // Truncates on i64 are assumed to be free.
290 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
291 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
292 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
293 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
296 if (SrcTy.isInteger()) {
298 ConvertCostTableLookup<MVT>(ARMIntegerConversionTbl,
299 array_lengthof(ARMIntegerConversionTbl),
300 ISD, DstTy.getSimpleVT(),
301 SrcTy.getSimpleVT());
303 return ARMIntegerConversionTbl[Idx].Cost;
307 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
310 unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
311 unsigned Index) const {
312 // Penalize inserting into an D-subregister. We end up with a three times
313 // lower estimated throughput on swift.
315 Opcode == Instruction::InsertElement &&
316 ValTy->isVectorTy() &&
317 ValTy->getScalarSizeInBits() <= 32)
320 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
323 unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
324 Type *CondTy) const {
326 int ISD = TLI->InstructionOpcodeToISD(Opcode);
327 // On NEON a a vector select gets lowered to vbsl.
328 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
329 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
333 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
336 unsigned ARMTTI::getAddressComputationCost(Type *Ty) const {
337 // In many cases the address computation is not merged into the instruction
342 unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
344 // We only handle costs of reverse shuffles for now.
345 if (Kind != SK_Reverse)
346 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
348 static const CostTblEntry<MVT> NEONShuffleTbl[] = {
349 // Reverse shuffle cost one instruction if we are shuffling within a double
350 // word (vrev) or two if we shuffle a quad word (vrev, vext).
351 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
352 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
353 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
354 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
356 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
357 { ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 },
358 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
359 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
362 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
364 int Idx = CostTableLookup<MVT>(NEONShuffleTbl, array_lengthof(NEONShuffleTbl),
365 ISD::VECTOR_SHUFFLE, LT.second);
367 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
369 return LT.first * NEONShuffleTbl[Idx].Cost;