1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "armtti"
19 #include "ARMTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeARMTTIPass(PassRegistry &);
35 class ARMTTI : public ImmutablePass, public TargetTransformInfo {
36 const ARMBaseTargetMachine *TM;
37 const ARMSubtarget *ST;
38 const ARMTargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 ARMTTI(const ARMBaseTargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeARMTTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
80 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
85 /// \name Vector TTI Implementations
88 unsigned getNumberOfRegisters(bool Vector) const {
95 if (ST->isThumb1Only())
100 unsigned getRegisterBitWidth(bool Vector) const {
110 unsigned getMaximumUnrollFactor() const {
111 // These are out of order CPUs:
112 if (ST->isCortexA15() || ST->isSwift())
117 unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
118 int Index, Type *SubTp) const;
120 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
123 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
125 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
127 unsigned getAddressComputationCost(Type *Val) const;
131 } // end anonymous namespace
133 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
134 "ARM Target Transform Info", true, true, false)
138 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
139 return new ARMTTI(TM);
143 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
144 assert(Ty->isIntegerTy());
146 unsigned Bits = Ty->getPrimitiveSizeInBits();
147 if (Bits == 0 || Bits > 32)
150 int32_t SImmVal = Imm.getSExtValue();
151 uint32_t ZImmVal = Imm.getZExtValue();
152 if (!ST->isThumb()) {
153 if ((SImmVal >= 0 && SImmVal < 65536) ||
154 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
155 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
157 return ST->hasV6T2Ops() ? 2 : 3;
158 } else if (ST->isThumb2()) {
159 if ((SImmVal >= 0 && SImmVal < 65536) ||
160 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
161 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
163 return ST->hasV6T2Ops() ? 2 : 3;
165 if (SImmVal >= 0 && SImmVal < 256)
167 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
169 // Load from constantpool.
175 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
177 int ISD = TLI->InstructionOpcodeToISD(Opcode);
178 assert(ISD && "Invalid opcode");
180 // Single to/from double precision conversions.
181 static const CostTblEntry<MVT> NEONFltDblTbl[] = {
182 // Vector fptrunc/fpext conversions.
183 { ISD::FP_ROUND, MVT::v2f64, 2 },
184 { ISD::FP_EXTEND, MVT::v2f32, 2 },
185 { ISD::FP_EXTEND, MVT::v4f32, 4 }
188 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
189 ISD == ISD::FP_EXTEND)) {
190 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
191 int Idx = CostTableLookup<MVT>(NEONFltDblTbl, array_lengthof(NEONFltDblTbl),
194 return LT.first * NEONFltDblTbl[Idx].Cost;
197 EVT SrcTy = TLI->getValueType(Src);
198 EVT DstTy = TLI->getValueType(Dst);
200 if (!SrcTy.isSimple() || !DstTy.isSimple())
201 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
203 // Some arithmetic, load and store operations have specific instructions
204 // to cast up/down their types automatically at no extra cost.
205 // TODO: Get these tables to know at least what the related operations are.
206 static const TypeConversionCostTblEntry<MVT> NEONVectorConversionTbl[] = {
207 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
208 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
209 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
210 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
211 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
212 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
214 // The number of vmovl instructions for the extension.
215 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
216 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 },
217 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
218 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 },
219 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
220 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 7 },
221 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
222 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
223 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
224 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
226 // Operations that we legalize using load/stores to the stack.
227 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4*1 + 16*2 + 2*1 },
228 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 2*1 + 8*2 + 1 },
230 // Vector float <-> i32 conversions.
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
232 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
234 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
235 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 },
236 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
237 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 },
238 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
239 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
240 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
241 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
242 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
243 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
244 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
245 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
246 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
247 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
248 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
249 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
250 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
251 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 },
252 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
253 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
255 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
256 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
257 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 },
258 { ISD::FP_TO_UINT, MVT::v4i8, MVT::v4f32, 3 },
259 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 },
260 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
262 // Vector double <-> i32 conversions.
263 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
264 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
266 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
267 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 },
268 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
269 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
270 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
271 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
273 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
274 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 },
275 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
276 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
277 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 },
278 { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 8 }
281 if (SrcTy.isVector() && ST->hasNEON()) {
282 int Idx = ConvertCostTableLookup<MVT>(NEONVectorConversionTbl,
283 array_lengthof(NEONVectorConversionTbl),
284 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
286 return NEONVectorConversionTbl[Idx].Cost;
289 // Scalar float to integer conversions.
290 static const TypeConversionCostTblEntry<MVT> NEONFloatConversionTbl[] = {
291 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 },
292 { ISD::FP_TO_UINT, MVT::i1, MVT::f32, 2 },
293 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 },
294 { ISD::FP_TO_UINT, MVT::i1, MVT::f64, 2 },
295 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 },
296 { ISD::FP_TO_UINT, MVT::i8, MVT::f32, 2 },
297 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 },
298 { ISD::FP_TO_UINT, MVT::i8, MVT::f64, 2 },
299 { ISD::FP_TO_SINT, MVT::i16, MVT::f32, 2 },
300 { ISD::FP_TO_UINT, MVT::i16, MVT::f32, 2 },
301 { ISD::FP_TO_SINT, MVT::i16, MVT::f64, 2 },
302 { ISD::FP_TO_UINT, MVT::i16, MVT::f64, 2 },
303 { ISD::FP_TO_SINT, MVT::i32, MVT::f32, 2 },
304 { ISD::FP_TO_UINT, MVT::i32, MVT::f32, 2 },
305 { ISD::FP_TO_SINT, MVT::i32, MVT::f64, 2 },
306 { ISD::FP_TO_UINT, MVT::i32, MVT::f64, 2 },
307 { ISD::FP_TO_SINT, MVT::i64, MVT::f32, 10 },
308 { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 10 },
309 { ISD::FP_TO_SINT, MVT::i64, MVT::f64, 10 },
310 { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 10 }
312 if (SrcTy.isFloatingPoint() && ST->hasNEON()) {
313 int Idx = ConvertCostTableLookup<MVT>(NEONFloatConversionTbl,
314 array_lengthof(NEONFloatConversionTbl),
315 ISD, DstTy.getSimpleVT(),
316 SrcTy.getSimpleVT());
318 return NEONFloatConversionTbl[Idx].Cost;
321 // Scalar integer to float conversions.
322 static const TypeConversionCostTblEntry<MVT> NEONIntegerConversionTbl[] = {
323 { ISD::SINT_TO_FP, MVT::f32, MVT::i1, 2 },
324 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 },
325 { ISD::SINT_TO_FP, MVT::f64, MVT::i1, 2 },
326 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 },
327 { ISD::SINT_TO_FP, MVT::f32, MVT::i8, 2 },
328 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 },
329 { ISD::SINT_TO_FP, MVT::f64, MVT::i8, 2 },
330 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 },
331 { ISD::SINT_TO_FP, MVT::f32, MVT::i16, 2 },
332 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 },
333 { ISD::SINT_TO_FP, MVT::f64, MVT::i16, 2 },
334 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 },
335 { ISD::SINT_TO_FP, MVT::f32, MVT::i32, 2 },
336 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 },
337 { ISD::SINT_TO_FP, MVT::f64, MVT::i32, 2 },
338 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 },
339 { ISD::SINT_TO_FP, MVT::f32, MVT::i64, 10 },
340 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 },
341 { ISD::SINT_TO_FP, MVT::f64, MVT::i64, 10 },
342 { ISD::UINT_TO_FP, MVT::f64, MVT::i64, 10 }
345 if (SrcTy.isInteger() && ST->hasNEON()) {
346 int Idx = ConvertCostTableLookup<MVT>(NEONIntegerConversionTbl,
347 array_lengthof(NEONIntegerConversionTbl),
348 ISD, DstTy.getSimpleVT(),
349 SrcTy.getSimpleVT());
351 return NEONIntegerConversionTbl[Idx].Cost;
354 // Scalar integer conversion costs.
355 static const TypeConversionCostTblEntry<MVT> ARMIntegerConversionTbl[] = {
356 // i16 -> i64 requires two dependent operations.
357 { ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 2 },
359 // Truncates on i64 are assumed to be free.
360 { ISD::TRUNCATE, MVT::i32, MVT::i64, 0 },
361 { ISD::TRUNCATE, MVT::i16, MVT::i64, 0 },
362 { ISD::TRUNCATE, MVT::i8, MVT::i64, 0 },
363 { ISD::TRUNCATE, MVT::i1, MVT::i64, 0 }
366 if (SrcTy.isInteger()) {
368 ConvertCostTableLookup<MVT>(ARMIntegerConversionTbl,
369 array_lengthof(ARMIntegerConversionTbl),
370 ISD, DstTy.getSimpleVT(),
371 SrcTy.getSimpleVT());
373 return ARMIntegerConversionTbl[Idx].Cost;
376 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
379 unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
380 unsigned Index) const {
381 // Penalize inserting into an D-subregister. We end up with a three times
382 // lower estimated throughput on swift.
384 Opcode == Instruction::InsertElement &&
385 ValTy->isVectorTy() &&
386 ValTy->getScalarSizeInBits() <= 32)
389 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);
392 unsigned ARMTTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
393 Type *CondTy) const {
395 int ISD = TLI->InstructionOpcodeToISD(Opcode);
396 // On NEON a a vector select gets lowered to vbsl.
397 if (ST->hasNEON() && ValTy->isVectorTy() && ISD == ISD::SELECT) {
398 // Lowering of some vector selects is currently far from perfect.
399 static const TypeConversionCostTblEntry<MVT> NEONVectorSelectTbl[] = {
400 { ISD::SELECT, MVT::v16i1, MVT::v16i16, 2*16 + 1 + 3*1 + 4*1 },
401 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 4*8 + 1*3 + 1*4 + 1*2 },
402 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
403 { ISD::SELECT, MVT::v4i1, MVT::v4i64, 4*4 + 1*2 + 1 },
404 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
405 { ISD::SELECT, MVT::v16i1, MVT::v16i64, 100 }
408 EVT SelCondTy = TLI->getValueType(CondTy);
409 EVT SelValTy = TLI->getValueType(ValTy);
410 int Idx = ConvertCostTableLookup<MVT>(NEONVectorSelectTbl,
411 array_lengthof(NEONVectorSelectTbl),
412 ISD, SelCondTy.getSimpleVT(),
413 SelValTy.getSimpleVT());
415 return NEONVectorSelectTbl[Idx].Cost;
417 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
421 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
424 unsigned ARMTTI::getAddressComputationCost(Type *Ty) const {
425 // In many cases the address computation is not merged into the instruction
430 unsigned ARMTTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
432 // We only handle costs of reverse shuffles for now.
433 if (Kind != SK_Reverse)
434 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
436 static const CostTblEntry<MVT> NEONShuffleTbl[] = {
437 // Reverse shuffle cost one instruction if we are shuffling within a double
438 // word (vrev) or two if we shuffle a quad word (vrev, vext).
439 { ISD::VECTOR_SHUFFLE, MVT::v2i32, 1 },
440 { ISD::VECTOR_SHUFFLE, MVT::v2f32, 1 },
441 { ISD::VECTOR_SHUFFLE, MVT::v2i64, 1 },
442 { ISD::VECTOR_SHUFFLE, MVT::v2f64, 1 },
444 { ISD::VECTOR_SHUFFLE, MVT::v4i32, 2 },
445 { ISD::VECTOR_SHUFFLE, MVT::v4f32, 2 },
446 { ISD::VECTOR_SHUFFLE, MVT::v8i16, 2 },
447 { ISD::VECTOR_SHUFFLE, MVT::v16i8, 2 }
450 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
452 int Idx = CostTableLookup<MVT>(NEONShuffleTbl, array_lengthof(NEONShuffleTbl),
453 ISD::VECTOR_SHUFFLE, LT.second);
455 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
457 return LT.first * NEONShuffleTbl[Idx].Cost;