1 //===-- ARMTargetTransformInfo.cpp - ARM specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// ARM target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "armtti"
19 #include "ARMTargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeARMTTIPass(PassRegistry &);
35 class ARMTTI : public ImmutablePass, public TargetTransformInfo {
36 const ARMBaseTargetMachine *TM;
37 const ARMSubtarget *ST;
38 const ARMTargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 ARMTTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 ARMTTI(const ARMBaseTargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeARMTTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
80 virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
85 /// \name Vector TTI Implementations
88 unsigned getNumberOfRegisters(bool Vector) const {
95 if (ST->isThumb1Only())
100 unsigned getRegisterBitWidth(bool Vector) const {
110 unsigned getMaximumUnrollFactor() const {
111 // These are out of order CPUs:
112 if (ST->isCortexA15() || ST->isSwift())
117 unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
120 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
124 } // end anonymous namespace
126 INITIALIZE_AG_PASS(ARMTTI, TargetTransformInfo, "armtti",
127 "ARM Target Transform Info", true, true, false)
131 llvm::createARMTargetTransformInfoPass(const ARMBaseTargetMachine *TM) {
132 return new ARMTTI(TM);
136 unsigned ARMTTI::getIntImmCost(const APInt &Imm, Type *Ty) const {
137 assert(Ty->isIntegerTy());
139 unsigned Bits = Ty->getPrimitiveSizeInBits();
140 if (Bits == 0 || Bits > 32)
143 int32_t SImmVal = Imm.getSExtValue();
144 uint32_t ZImmVal = Imm.getZExtValue();
145 if (!ST->isThumb()) {
146 if ((SImmVal >= 0 && SImmVal < 65536) ||
147 (ARM_AM::getSOImmVal(ZImmVal) != -1) ||
148 (ARM_AM::getSOImmVal(~ZImmVal) != -1))
150 return ST->hasV6T2Ops() ? 2 : 3;
151 } else if (ST->isThumb2()) {
152 if ((SImmVal >= 0 && SImmVal < 65536) ||
153 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) ||
154 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1))
156 return ST->hasV6T2Ops() ? 2 : 3;
158 if (SImmVal >= 0 && SImmVal < 256)
160 if ((~ZImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
162 // Load from constantpool.
168 unsigned ARMTTI::getCastInstrCost(unsigned Opcode, Type *Dst,
170 int ISD = TLI->InstructionOpcodeToISD(Opcode);
171 assert(ISD && "Invalid opcode");
173 EVT SrcTy = TLI->getValueType(Src);
174 EVT DstTy = TLI->getValueType(Dst);
176 if (!SrcTy.isSimple() || !DstTy.isSimple())
177 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
179 // Some arithmetic, load and store operations have specific instructions
180 // to cast up/down their types automatically at no extra cost
181 // TODO: Get these tables to know at least what the related operations are
182 static const TypeConversionCostTblEntry<MVT> NEONConversionTbl[] = {
183 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
184 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
185 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
186 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
187 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
188 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
192 int Idx = ConvertCostTableLookup<MVT>(NEONConversionTbl,
193 array_lengthof(NEONConversionTbl),
194 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
196 return NEONConversionTbl[Idx].Cost;
199 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
202 unsigned ARMTTI::getVectorInstrCost(unsigned Opcode, Type *ValTy,
203 unsigned Index) const {
204 // Penalize inserting into an D-subregister.
206 Opcode == Instruction::InsertElement &&
207 ValTy->isVectorTy() &&
208 ValTy->getScalarSizeInBits() <= 32)
211 return TargetTransformInfo::getVectorInstrCost(Opcode, ValTy, Index);