1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
21 #include "ARMTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 #include "llvm/Target/TargetLowering.h"
28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
29 typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
30 typedef TargetTransformInfo TTI;
33 const ARMSubtarget *ST;
34 const ARMTargetLowering *TLI;
36 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
37 /// are set if the result needs to be inserted and/or extracted from vectors.
38 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
40 const ARMSubtarget *getST() const { return ST; }
41 const ARMTargetLowering *getTLI() const { return TLI; }
44 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, Function &F)
45 : BaseT(TM), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {}
47 // Provide value semantics. MSVC requires that we spell all of these out.
48 ARMTTIImpl(const ARMTTIImpl &Arg)
49 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
50 ARMTTIImpl(ARMTTIImpl &&Arg)
51 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
52 TLI(std::move(Arg.TLI)) {}
53 ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
54 BaseT::operator=(static_cast<const BaseT &>(RHS));
59 ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
60 BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
61 ST = std::move(RHS.ST);
62 TLI = std::move(RHS.TLI);
66 /// \name Scalar TTI Implementations
69 using BaseT::getIntImmCost;
70 unsigned getIntImmCost(const APInt &Imm, Type *Ty);
74 /// \name Vector TTI Implementations
77 unsigned getNumberOfRegisters(bool Vector) {
84 if (ST->isThumb1Only())
89 unsigned getRegisterBitWidth(bool Vector) {
99 unsigned getMaxInterleaveFactor() {
100 // These are out of order CPUs:
101 if (ST->isCortexA15() || ST->isSwift())
106 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
109 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
111 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
113 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
115 unsigned getAddressComputationCost(Type *Val, bool IsComplex);
117 unsigned getFPOpCost(Type *Ty);
119 unsigned getArithmeticInstrCost(
120 unsigned Opcode, Type *Ty,
121 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
122 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
123 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
124 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
126 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
127 unsigned AddressSpace);
132 } // end namespace llvm