1 //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file a TargetTransformInfo::Concept conforming object specific to the
11 /// ARM target machine. It uses the target's detailed information to
12 /// provide more precise answers to certain TTI queries, while letting the
13 /// target independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
21 #include "ARMTargetMachine.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/BasicTTIImpl.h"
24 #include "llvm/Target/TargetLowering.h"
28 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
29 typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
30 typedef TargetTransformInfo TTI;
32 const ARMSubtarget *ST;
33 const ARMTargetLowering *TLI;
35 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
36 /// are set if the result needs to be inserted and/or extracted from vectors.
37 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
40 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM = nullptr)
41 : BaseT(TM), ST(TM ? TM->getSubtargetImpl() : nullptr),
42 TLI(ST ? ST->getTargetLowering() : nullptr) {}
44 // Provide value semantics. MSVC requires that we spell all of these out.
45 ARMTTIImpl(const ARMTTIImpl &Arg)
46 : BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
47 ARMTTIImpl(ARMTTIImpl &&Arg)
48 : BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
49 TLI(std::move(Arg.TLI)) {}
50 ARMTTIImpl &operator=(const ARMTTIImpl &RHS) {
51 BaseT::operator=(static_cast<const BaseT &>(RHS));
56 ARMTTIImpl &operator=(ARMTTIImpl &&RHS) {
57 BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
58 ST = std::move(RHS.ST);
59 TLI = std::move(RHS.TLI);
63 /// \name Scalar TTI Implementations
66 using BaseT::getIntImmCost;
67 unsigned getIntImmCost(const APInt &Imm, Type *Ty);
71 /// \name Vector TTI Implementations
74 unsigned getNumberOfRegisters(bool Vector) {
81 if (ST->isThumb1Only())
86 unsigned getRegisterBitWidth(bool Vector) {
96 unsigned getMaxInterleaveFactor() {
97 // These are out of order CPUs:
98 if (ST->isCortexA15() || ST->isSwift())
103 unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
106 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
108 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
110 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
112 unsigned getAddressComputationCost(Type *Val, bool IsComplex);
114 unsigned getArithmeticInstrCost(
115 unsigned Opcode, Type *Ty,
116 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
117 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
118 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
119 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
121 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
122 unsigned AddressSpace);
127 } // end namespace llvm