1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
27 // The shift types for register controlled shifts in arm memory addressing
39 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
46 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
48 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
50 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
52 ARMOperand *MaybeParseRegister(bool ParseWriteBack);
53 ARMOperand *ParseRegisterList();
54 ARMOperand *ParseMemory();
56 bool ParseMemoryOffsetReg(bool &Negative,
57 bool &OffsetRegShifted,
58 enum ShiftType &ShiftType,
59 const MCExpr *&ShiftAmount,
60 const MCExpr *&Offset,
65 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 ARMOperand *ParseOperand();
69 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
73 bool ParseDirectiveThumbFunc(SMLoc L);
75 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
83 /// @name Auto-generated Match Functions
86 #define GET_ASSEMBLER_HEADER
87 #include "ARMGenAsmMatcher.inc"
93 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
94 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
96 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
97 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
99 virtual bool ParseDirective(AsmToken DirectiveID);
101 } // end anonymous namespace
105 /// ARMOperand - Instances of this class represent a parsed ARM machine
107 struct ARMOperand : public MCParsedAsmOperand {
117 SMLoc StartLoc, EndLoc;
121 ARMCC::CondCodes Val;
138 // This is for all forms of ARM address expressions
141 unsigned OffsetRegNum; // used when OffsetIsReg is true
142 const MCExpr *Offset; // used when OffsetIsReg is false
143 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
144 enum ShiftType ShiftType; // used when OffsetRegShifted is true
146 OffsetRegShifted : 1, // only used when OffsetIsReg is true
150 Negative : 1, // only used when OffsetIsReg is true
156 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
158 StartLoc = o.StartLoc;
179 /// getStartLoc - Get the location of the first token of this operand.
180 SMLoc getStartLoc() const { return StartLoc; }
181 /// getEndLoc - Get the location of the last token of this operand.
182 SMLoc getEndLoc() const { return EndLoc; }
184 ARMCC::CondCodes getCondCode() const {
185 assert(Kind == CondCode && "Invalid access!");
189 StringRef getToken() const {
190 assert(Kind == Token && "Invalid access!");
191 return StringRef(Tok.Data, Tok.Length);
194 unsigned getReg() const {
195 assert(Kind == Register && "Invalid access!");
199 const MCExpr *getImm() const {
200 assert(Kind == Immediate && "Invalid access!");
204 bool isCondCode() const { return Kind == CondCode; }
205 bool isImm() const { return Kind == Immediate; }
206 bool isReg() const { return Kind == Register; }
207 bool isToken() const { return Kind == Token; }
208 bool isMemory() const { return Kind == Memory; }
210 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
211 // Add as immediates when possible. Null MCExpr = 0.
213 Inst.addOperand(MCOperand::CreateImm(0));
214 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
215 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
217 Inst.addOperand(MCOperand::CreateExpr(Expr));
220 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
221 assert(N == 2 && "Invalid number of operands!");
222 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
223 // FIXME: What belongs here?
224 Inst.addOperand(MCOperand::CreateReg(0));
227 void addRegOperands(MCInst &Inst, unsigned N) const {
228 assert(N == 1 && "Invalid number of operands!");
229 Inst.addOperand(MCOperand::CreateReg(getReg()));
232 void addImmOperands(MCInst &Inst, unsigned N) const {
233 assert(N == 1 && "Invalid number of operands!");
234 addExpr(Inst, getImm());
238 bool isMemMode5() const {
239 // FIXME: Is this right? What about postindexed and Writeback?
240 if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
241 Mem.Preindexed || Mem.Negative)
247 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
248 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
250 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
251 assert(!Mem.OffsetIsReg && "invalid mode 5 operand");
252 addExpr(Inst, Mem.Offset);
255 virtual void dump(raw_ostream &OS) const;
257 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
258 ARMOperand *Op = new ARMOperand(CondCode);
265 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
266 ARMOperand *Op = new ARMOperand(Token);
267 Op->Tok.Data = Str.data();
268 Op->Tok.Length = Str.size();
274 static ARMOperand *CreateReg(unsigned RegNum, bool Writeback, SMLoc S,
276 ARMOperand *Op = new ARMOperand(Register);
277 Op->Reg.RegNum = RegNum;
278 Op->Reg.Writeback = Writeback;
284 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
285 ARMOperand *Op = new ARMOperand(Immediate);
292 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
293 const MCExpr *Offset, unsigned OffsetRegNum,
294 bool OffsetRegShifted, enum ShiftType ShiftType,
295 const MCExpr *ShiftAmount, bool Preindexed,
296 bool Postindexed, bool Negative, bool Writeback,
298 ARMOperand *Op = new ARMOperand(Memory);
299 Op->Mem.BaseRegNum = BaseRegNum;
300 Op->Mem.OffsetIsReg = OffsetIsReg;
301 Op->Mem.Offset = Offset;
302 Op->Mem.OffsetRegNum = OffsetRegNum;
303 Op->Mem.OffsetRegShifted = OffsetRegShifted;
304 Op->Mem.ShiftType = ShiftType;
305 Op->Mem.ShiftAmount = ShiftAmount;
306 Op->Mem.Preindexed = Preindexed;
307 Op->Mem.Postindexed = Postindexed;
308 Op->Mem.Negative = Negative;
309 Op->Mem.Writeback = Writeback;
317 ARMOperand(KindTy K) : Kind(K) {}
320 } // end anonymous namespace.
322 void ARMOperand::dump(raw_ostream &OS) const {
325 OS << ARMCondCodeToString(getCondCode());
334 OS << "<register " << getReg() << ">";
337 OS << "'" << getToken() << "'";
342 /// @name Auto-generated Match Functions
345 static unsigned MatchRegisterName(StringRef Name);
349 /// Try to parse a register name. The token must be an Identifier when called,
350 /// and if it is a register name the token is eaten and a Reg operand is created
351 /// and returned. Otherwise return null.
353 /// TODO this is likely to change to allow different register types and or to
354 /// parse for a specific register type.
355 ARMOperand *ARMAsmParser::MaybeParseRegister(bool ParseWriteBack) {
357 const AsmToken &Tok = Parser.getTok();
358 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
360 // FIXME: Validate register for the current architecture; we have to do
361 // validation later, so maybe there is no need for this here.
364 RegNum = MatchRegisterName(Tok.getString());
370 Parser.Lex(); // Eat identifier token.
372 E = Parser.getTok().getLoc();
374 bool Writeback = false;
375 if (ParseWriteBack) {
376 const AsmToken &ExclaimTok = Parser.getTok();
377 if (ExclaimTok.is(AsmToken::Exclaim)) {
378 E = ExclaimTok.getLoc();
380 Parser.Lex(); // Eat exclaim token
384 return ARMOperand::CreateReg(RegNum, Writeback, S, E);
387 /// Parse a register list, return it if successful else return null. The first
388 /// token must be a '{' when called.
389 ARMOperand *ARMAsmParser::ParseRegisterList() {
391 assert(Parser.getTok().is(AsmToken::LCurly) &&
392 "Token is not an Left Curly Brace");
393 S = Parser.getTok().getLoc();
394 Parser.Lex(); // Eat left curly brace token.
396 const AsmToken &RegTok = Parser.getTok();
397 SMLoc RegLoc = RegTok.getLoc();
398 if (RegTok.isNot(AsmToken::Identifier)) {
399 Error(RegLoc, "register expected");
402 int RegNum = MatchRegisterName(RegTok.getString());
404 Error(RegLoc, "register expected");
408 Parser.Lex(); // Eat identifier token.
409 unsigned RegList = 1 << RegNum;
411 int HighRegNum = RegNum;
412 // TODO ranges like "{Rn-Rm}"
413 while (Parser.getTok().is(AsmToken::Comma)) {
414 Parser.Lex(); // Eat comma token.
416 const AsmToken &RegTok = Parser.getTok();
417 SMLoc RegLoc = RegTok.getLoc();
418 if (RegTok.isNot(AsmToken::Identifier)) {
419 Error(RegLoc, "register expected");
422 int RegNum = MatchRegisterName(RegTok.getString());
424 Error(RegLoc, "register expected");
428 if (RegList & (1 << RegNum))
429 Warning(RegLoc, "register duplicated in register list");
430 else if (RegNum <= HighRegNum)
431 Warning(RegLoc, "register not in ascending order in register list");
432 RegList |= 1 << RegNum;
435 Parser.Lex(); // Eat identifier token.
437 const AsmToken &RCurlyTok = Parser.getTok();
438 if (RCurlyTok.isNot(AsmToken::RCurly)) {
439 Error(RCurlyTok.getLoc(), "'}' expected");
442 E = RCurlyTok.getLoc();
443 Parser.Lex(); // Eat left curly brace token.
445 // FIXME: Need to return an operand!
446 Error(E, "FIXME: register list parsing not implemented");
450 /// Parse an arm memory expression, return false if successful else return true
451 /// or an error. The first token must be a '[' when called.
452 /// TODO Only preindexing and postindexing addressing are started, unindexed
453 /// with option, etc are still to do.
454 ARMOperand *ARMAsmParser::ParseMemory() {
456 assert(Parser.getTok().is(AsmToken::LBrac) &&
457 "Token is not an Left Bracket");
458 S = Parser.getTok().getLoc();
459 Parser.Lex(); // Eat left bracket token.
461 const AsmToken &BaseRegTok = Parser.getTok();
462 if (BaseRegTok.isNot(AsmToken::Identifier)) {
463 Error(BaseRegTok.getLoc(), "register expected");
467 if (ARMOperand *Op = MaybeParseRegister(false)) {
468 BaseRegNum = Op->getReg();
471 Error(BaseRegTok.getLoc(), "register expected");
475 bool Preindexed = false;
476 bool Postindexed = false;
477 bool OffsetIsReg = false;
478 bool Negative = false;
479 bool Writeback = false;
481 // First look for preindexed address forms, that is after the "[Rn" we now
482 // have to see if the next token is a comma.
483 const AsmToken &Tok = Parser.getTok();
484 if (Tok.is(AsmToken::Comma)) {
486 Parser.Lex(); // Eat comma token.
488 bool OffsetRegShifted;
489 enum ShiftType ShiftType;
490 const MCExpr *ShiftAmount;
491 const MCExpr *Offset;
492 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
493 Offset, OffsetIsReg, OffsetRegNum, E))
495 const AsmToken &RBracTok = Parser.getTok();
496 if (RBracTok.isNot(AsmToken::RBrac)) {
497 Error(RBracTok.getLoc(), "']' expected");
500 E = RBracTok.getLoc();
501 Parser.Lex(); // Eat right bracket token.
503 const AsmToken &ExclaimTok = Parser.getTok();
504 if (ExclaimTok.is(AsmToken::Exclaim)) {
505 E = ExclaimTok.getLoc();
507 Parser.Lex(); // Eat exclaim token
509 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
510 OffsetRegShifted, ShiftType, ShiftAmount,
511 Preindexed, Postindexed, Negative, Writeback,
514 // The "[Rn" we have so far was not followed by a comma.
515 else if (Tok.is(AsmToken::RBrac)) {
516 // This is a post indexing addressing forms, that is a ']' follows after
521 Parser.Lex(); // Eat right bracket token.
523 int OffsetRegNum = 0;
524 bool OffsetRegShifted = false;
525 enum ShiftType ShiftType;
526 const MCExpr *ShiftAmount;
527 const MCExpr *Offset = 0;
529 const AsmToken &NextTok = Parser.getTok();
530 if (NextTok.isNot(AsmToken::EndOfStatement)) {
531 if (NextTok.isNot(AsmToken::Comma)) {
532 Error(NextTok.getLoc(), "',' expected");
535 Parser.Lex(); // Eat comma token.
536 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
537 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
542 return ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
543 OffsetRegShifted, ShiftType, ShiftAmount,
544 Preindexed, Postindexed, Negative, Writeback,
551 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
552 /// we will parse the following (were +/- means that a plus or minus is
557 /// we return false on success or an error otherwise.
558 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
559 bool &OffsetRegShifted,
560 enum ShiftType &ShiftType,
561 const MCExpr *&ShiftAmount,
562 const MCExpr *&Offset,
567 OffsetRegShifted = false;
570 const AsmToken &NextTok = Parser.getTok();
571 E = NextTok.getLoc();
572 if (NextTok.is(AsmToken::Plus))
573 Parser.Lex(); // Eat plus token.
574 else if (NextTok.is(AsmToken::Minus)) {
576 Parser.Lex(); // Eat minus token
578 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
579 const AsmToken &OffsetRegTok = Parser.getTok();
580 if (OffsetRegTok.is(AsmToken::Identifier)) {
581 if (ARMOperand *Op = MaybeParseRegister(false)) {
584 OffsetRegNum = Op->getReg();
588 // If we parsed a register as the offset then their can be a shift after that
589 if (OffsetRegNum != -1) {
590 // Look for a comma then a shift
591 const AsmToken &Tok = Parser.getTok();
592 if (Tok.is(AsmToken::Comma)) {
593 Parser.Lex(); // Eat comma token.
595 const AsmToken &Tok = Parser.getTok();
596 if (ParseShift(ShiftType, ShiftAmount, E))
597 return Error(Tok.getLoc(), "shift expected");
598 OffsetRegShifted = true;
601 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
602 // Look for #offset following the "[Rn," or "[Rn],"
603 const AsmToken &HashTok = Parser.getTok();
604 if (HashTok.isNot(AsmToken::Hash))
605 return Error(HashTok.getLoc(), "'#' expected");
607 Parser.Lex(); // Eat hash token.
609 if (getParser().ParseExpression(Offset))
611 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
616 /// ParseShift as one of these two:
617 /// ( lsl | lsr | asr | ror ) , # shift_amount
619 /// and returns true if it parses a shift otherwise it returns false.
620 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
622 const AsmToken &Tok = Parser.getTok();
623 if (Tok.isNot(AsmToken::Identifier))
625 StringRef ShiftName = Tok.getString();
626 if (ShiftName == "lsl" || ShiftName == "LSL")
628 else if (ShiftName == "lsr" || ShiftName == "LSR")
630 else if (ShiftName == "asr" || ShiftName == "ASR")
632 else if (ShiftName == "ror" || ShiftName == "ROR")
634 else if (ShiftName == "rrx" || ShiftName == "RRX")
638 Parser.Lex(); // Eat shift type token.
644 // Otherwise, there must be a '#' and a shift amount.
645 const AsmToken &HashTok = Parser.getTok();
646 if (HashTok.isNot(AsmToken::Hash))
647 return Error(HashTok.getLoc(), "'#' expected");
648 Parser.Lex(); // Eat hash token.
650 if (getParser().ParseExpression(ShiftAmount))
656 /// Parse a arm instruction operand. For now this parses the operand regardless
658 ARMOperand *ARMAsmParser::ParseOperand() {
661 switch (getLexer().getKind()) {
662 case AsmToken::Identifier:
663 if (ARMOperand *Op = MaybeParseRegister(true))
666 // This was not a register so parse other operands that start with an
667 // identifier (like labels) as expressions and create them as immediates.
669 S = Parser.getTok().getLoc();
670 if (getParser().ParseExpression(IdVal))
672 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
673 return ARMOperand::CreateImm(IdVal, S, E);
674 case AsmToken::LBrac:
675 return ParseMemory();
676 case AsmToken::LCurly:
677 return ParseRegisterList();
680 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
681 S = Parser.getTok().getLoc();
683 const MCExpr *ImmVal;
684 if (getParser().ParseExpression(ImmVal))
686 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
687 return ARMOperand::CreateImm(ImmVal, S, E);
689 Error(Parser.getTok().getLoc(), "unexpected token in operand");
694 /// Parse an arm instruction mnemonic followed by its operands.
695 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
696 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
697 // Create the leading tokens for the mnemonic, split by '.' characters.
698 size_t Start = 0, Next = Name.find('.');
699 StringRef Head = Name.slice(Start, Next);
701 // Determine the predicate, if any.
703 // FIXME: We need a way to check whether a prefix supports predication,
704 // otherwise we will end up with an ambiguity for instructions that happen to
705 // end with a predicate name.
706 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
707 .Case("eq", ARMCC::EQ)
708 .Case("ne", ARMCC::NE)
709 .Case("hs", ARMCC::HS)
710 .Case("lo", ARMCC::LO)
711 .Case("mi", ARMCC::MI)
712 .Case("pl", ARMCC::PL)
713 .Case("vs", ARMCC::VS)
714 .Case("vc", ARMCC::VC)
715 .Case("hi", ARMCC::HI)
716 .Case("ls", ARMCC::LS)
717 .Case("ge", ARMCC::GE)
718 .Case("lt", ARMCC::LT)
719 .Case("gt", ARMCC::GT)
720 .Case("le", ARMCC::LE)
721 .Case("al", ARMCC::AL)
725 Head = Head.slice(0, Head.size() - 2);
729 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
730 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc));
732 // Add the remaining tokens in the mnemonic.
733 while (Next != StringRef::npos) {
735 Next = Name.find('.', Start + 1);
736 Head = Name.slice(Start, Next);
738 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
741 // Read the remaining operands.
742 if (getLexer().isNot(AsmToken::EndOfStatement)) {
743 // Read the first operand.
744 if (ARMOperand *Op = ParseOperand())
745 Operands.push_back(Op);
747 Parser.EatToEndOfStatement();
751 while (getLexer().is(AsmToken::Comma)) {
752 Parser.Lex(); // Eat the comma.
754 // Parse and remember the operand.
755 if (ARMOperand *Op = ParseOperand())
756 Operands.push_back(Op);
758 Parser.EatToEndOfStatement();
764 if (getLexer().isNot(AsmToken::EndOfStatement)) {
765 Parser.EatToEndOfStatement();
766 return TokError("unexpected token in argument list");
768 Parser.Lex(); // Consume the EndOfStatement
773 MatchAndEmitInstruction(SMLoc IDLoc,
774 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
778 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo)) {
780 Out.EmitInstruction(Inst);
783 case Match_MissingFeature:
784 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
786 case Match_InvalidOperand: {
787 SMLoc ErrorLoc = IDLoc;
788 if (ErrorInfo != ~0U) {
789 if (ErrorInfo >= Operands.size())
790 return Error(IDLoc, "too few operands for instruction");
792 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
793 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
796 return Error(ErrorLoc, "invalid operand for instruction");
798 case Match_MnemonicFail:
799 return Error(IDLoc, "unrecognized instruction mnemonic");
802 llvm_unreachable("Implement any new match types added!");
807 /// ParseDirective parses the arm specific directives
808 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
809 StringRef IDVal = DirectiveID.getIdentifier();
810 if (IDVal == ".word")
811 return ParseDirectiveWord(4, DirectiveID.getLoc());
812 else if (IDVal == ".thumb")
813 return ParseDirectiveThumb(DirectiveID.getLoc());
814 else if (IDVal == ".thumb_func")
815 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
816 else if (IDVal == ".code")
817 return ParseDirectiveCode(DirectiveID.getLoc());
818 else if (IDVal == ".syntax")
819 return ParseDirectiveSyntax(DirectiveID.getLoc());
823 /// ParseDirectiveWord
824 /// ::= .word [ expression (, expression)* ]
825 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
826 if (getLexer().isNot(AsmToken::EndOfStatement)) {
829 if (getParser().ParseExpression(Value))
832 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
834 if (getLexer().is(AsmToken::EndOfStatement))
837 // FIXME: Improve diagnostic.
838 if (getLexer().isNot(AsmToken::Comma))
839 return Error(L, "unexpected token in directive");
848 /// ParseDirectiveThumb
850 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
851 if (getLexer().isNot(AsmToken::EndOfStatement))
852 return Error(L, "unexpected token in directive");
855 // TODO: set thumb mode
856 // TODO: tell the MC streamer the mode
857 // getParser().getStreamer().Emit???();
861 /// ParseDirectiveThumbFunc
862 /// ::= .thumbfunc symbol_name
863 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
864 const AsmToken &Tok = Parser.getTok();
865 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
866 return Error(L, "unexpected token in .syntax directive");
867 Parser.Lex(); // Consume the identifier token.
869 if (getLexer().isNot(AsmToken::EndOfStatement))
870 return Error(L, "unexpected token in directive");
873 // TODO: mark symbol as a thumb symbol
874 // getParser().getStreamer().Emit???();
878 /// ParseDirectiveSyntax
879 /// ::= .syntax unified | divided
880 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
881 const AsmToken &Tok = Parser.getTok();
882 if (Tok.isNot(AsmToken::Identifier))
883 return Error(L, "unexpected token in .syntax directive");
884 StringRef Mode = Tok.getString();
885 if (Mode == "unified" || Mode == "UNIFIED")
887 else if (Mode == "divided" || Mode == "DIVIDED")
890 return Error(L, "unrecognized syntax mode in .syntax directive");
892 if (getLexer().isNot(AsmToken::EndOfStatement))
893 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
896 // TODO tell the MC streamer the mode
897 // getParser().getStreamer().Emit???();
901 /// ParseDirectiveCode
902 /// ::= .code 16 | 32
903 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
904 const AsmToken &Tok = Parser.getTok();
905 if (Tok.isNot(AsmToken::Integer))
906 return Error(L, "unexpected token in .code directive");
907 int64_t Val = Parser.getTok().getIntVal();
913 return Error(L, "invalid operand to .code directive");
915 if (getLexer().isNot(AsmToken::EndOfStatement))
916 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
919 // TODO tell the MC streamer the mode
920 // getParser().getStreamer().Emit???();
924 extern "C" void LLVMInitializeARMAsmLexer();
926 /// Force static initialization.
927 extern "C" void LLVMInitializeARMAsmParser() {
928 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
929 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
930 LLVMInitializeARMAsmLexer();
933 #define GET_REGISTER_MATCHER
934 #define GET_MATCHER_IMPLEMENTATION
935 #include "ARMGenAsmMatcher.inc"