1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCParser/MCAsmLexer.h"
26 #include "llvm/MC/MCParser/MCAsmParser.h"
27 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/SourceMgr.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 bool Warning(SMLoc L, const Twine &Msg,
86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87 return Parser.Warning(L, Msg, Ranges);
89 bool Error(SMLoc L, const Twine &Msg,
90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91 return Parser.Error(L, Msg, Ranges);
94 int tryParseRegister();
95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102 unsigned &ShiftAmount);
103 bool parseDirectiveWord(unsigned Size, SMLoc L);
104 bool parseDirectiveThumb(SMLoc L);
105 bool parseDirectiveARM(SMLoc L);
106 bool parseDirectiveThumbFunc(SMLoc L);
107 bool parseDirectiveCode(SMLoc L);
108 bool parseDirectiveSyntax(SMLoc L);
109 bool parseDirectiveReq(StringRef Name, SMLoc L);
110 bool parseDirectiveUnreq(SMLoc L);
111 bool parseDirectiveArch(SMLoc L);
112 bool parseDirectiveEabiAttr(SMLoc L);
114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115 bool &CarrySetting, unsigned &ProcessorIMod,
117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118 bool &CanAcceptPredicationCode);
120 bool isThumb() const {
121 // FIXME: Can tablegen auto-generate this?
122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
124 bool isThumbOne() const {
125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
127 bool isThumbTwo() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
130 bool hasV6Ops() const {
131 return STI.getFeatureBits() & ARM::HasV6Ops;
133 bool hasV7Ops() const {
134 return STI.getFeatureBits() & ARM::HasV7Ops;
137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138 setAvailableFeatures(FB);
140 bool isMClass() const {
141 return STI.getFeatureBits() & ARM::FeatureMClass;
144 /// @name Auto-generated Match Functions
147 #define GET_ASSEMBLER_HEADER
148 #include "ARMGenAsmMatcher.inc"
152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseCoprocNumOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseCoprocRegOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseCoprocOptionOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseMemBarrierOptOperand(
160 SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseProcIFlagsOperand(
162 SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseMSRMaskOperand(
164 SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166 StringRef Op, int Low, int High);
167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168 return parsePKHImm(O, "lsl", 0, 31);
170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "asr", 1, 32);
173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
183 // Asm Match Converter Methods
184 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
185 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
186 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
187 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
189 const SmallVectorImpl<MCParsedAsmOperand*> &);
190 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
191 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
193 const SmallVectorImpl<MCParsedAsmOperand*> &);
194 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
195 const SmallVectorImpl<MCParsedAsmOperand*> &);
196 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
197 const SmallVectorImpl<MCParsedAsmOperand*> &);
198 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
199 const SmallVectorImpl<MCParsedAsmOperand*> &);
200 void cvtLdExtTWriteBackImm(MCInst &Inst,
201 const SmallVectorImpl<MCParsedAsmOperand*> &);
202 void cvtLdExtTWriteBackReg(MCInst &Inst,
203 const SmallVectorImpl<MCParsedAsmOperand*> &);
204 void cvtStExtTWriteBackImm(MCInst &Inst,
205 const SmallVectorImpl<MCParsedAsmOperand*> &);
206 void cvtStExtTWriteBackReg(MCInst &Inst,
207 const SmallVectorImpl<MCParsedAsmOperand*> &);
208 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
209 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
210 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
211 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 void cvtThumbMultiply(MCInst &Inst,
213 const SmallVectorImpl<MCParsedAsmOperand*> &);
214 void cvtVLDwbFixed(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &);
216 void cvtVLDwbRegister(MCInst &Inst,
217 const SmallVectorImpl<MCParsedAsmOperand*> &);
218 void cvtVSTwbFixed(MCInst &Inst,
219 const SmallVectorImpl<MCParsedAsmOperand*> &);
220 void cvtVSTwbRegister(MCInst &Inst,
221 const SmallVectorImpl<MCParsedAsmOperand*> &);
222 bool validateInstruction(MCInst &Inst,
223 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
224 bool processInstruction(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
226 bool shouldOmitCCOutOperand(StringRef Mnemonic,
227 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230 enum ARMMatchResultTy {
231 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
232 Match_RequiresNotITBlock,
234 Match_RequiresThumb2,
235 #define GET_OPERAND_DIAGNOSTIC_TYPES
236 #include "ARMGenAsmMatcher.inc"
240 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
241 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
242 MCAsmParserExtension::Initialize(_Parser);
244 // Cache the MCRegisterInfo.
245 MRI = &getContext().getRegisterInfo();
247 // Initialize the set of available features.
248 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
250 // Not in an ITBlock to start with.
251 ITState.CurPosition = ~0U;
254 // Implementation of the MCTargetAsmParser interface:
255 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
256 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
258 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
259 bool ParseDirective(AsmToken DirectiveID);
261 unsigned checkTargetMatchPredicate(MCInst &Inst);
263 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
264 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
265 MCStreamer &Out, unsigned &ErrorInfo,
266 bool MatchingInlineAsm);
268 } // end anonymous namespace
272 /// ARMOperand - Instances of this class represent a parsed ARM machine
274 class ARMOperand : public MCParsedAsmOperand {
294 k_VectorListAllLanes,
300 k_BitfieldDescriptor,
304 SMLoc StartLoc, EndLoc;
305 SmallVector<unsigned, 8> Registers;
309 ARMCC::CondCodes Val;
329 ARM_PROC::IFlags Val;
345 // A vector register list is a sequential list of 1 to 4 registers.
361 /// Combined record for all forms of ARM address expressions.
364 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
366 const MCConstantExpr *OffsetImm; // Offset immediate value
367 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
368 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
369 unsigned ShiftImm; // shift for OffsetReg.
370 unsigned Alignment; // 0 = no alignment specified
371 // n = alignment in bytes (2, 4, 8, 16, or 32)
372 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
378 ARM_AM::ShiftOpc ShiftTy;
387 ARM_AM::ShiftOpc ShiftTy;
393 ARM_AM::ShiftOpc ShiftTy;
406 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
408 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
410 StartLoc = o.StartLoc;
427 case k_DPRRegisterList:
428 case k_SPRRegisterList:
429 Registers = o.Registers;
432 case k_VectorListAllLanes:
433 case k_VectorListIndexed:
434 VectorList = o.VectorList;
441 CoprocOption = o.CoprocOption;
446 case k_MemBarrierOpt:
452 case k_PostIndexRegister:
453 PostIdxReg = o.PostIdxReg;
461 case k_ShifterImmediate:
462 ShifterImm = o.ShifterImm;
464 case k_ShiftedRegister:
465 RegShiftedReg = o.RegShiftedReg;
467 case k_ShiftedImmediate:
468 RegShiftedImm = o.RegShiftedImm;
470 case k_RotateImmediate:
473 case k_BitfieldDescriptor:
474 Bitfield = o.Bitfield;
477 VectorIndex = o.VectorIndex;
482 /// getStartLoc - Get the location of the first token of this operand.
483 SMLoc getStartLoc() const { return StartLoc; }
484 /// getEndLoc - Get the location of the last token of this operand.
485 SMLoc getEndLoc() const { return EndLoc; }
486 /// getLocRange - Get the range between the first and last token of this
488 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
490 ARMCC::CondCodes getCondCode() const {
491 assert(Kind == k_CondCode && "Invalid access!");
495 unsigned getCoproc() const {
496 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
500 StringRef getToken() const {
501 assert(Kind == k_Token && "Invalid access!");
502 return StringRef(Tok.Data, Tok.Length);
505 unsigned getReg() const {
506 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
510 const SmallVectorImpl<unsigned> &getRegList() const {
511 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
512 Kind == k_SPRRegisterList) && "Invalid access!");
516 const MCExpr *getImm() const {
517 assert(isImm() && "Invalid access!");
521 unsigned getVectorIndex() const {
522 assert(Kind == k_VectorIndex && "Invalid access!");
523 return VectorIndex.Val;
526 ARM_MB::MemBOpt getMemBarrierOpt() const {
527 assert(Kind == k_MemBarrierOpt && "Invalid access!");
531 ARM_PROC::IFlags getProcIFlags() const {
532 assert(Kind == k_ProcIFlags && "Invalid access!");
536 unsigned getMSRMask() const {
537 assert(Kind == k_MSRMask && "Invalid access!");
541 bool isCoprocNum() const { return Kind == k_CoprocNum; }
542 bool isCoprocReg() const { return Kind == k_CoprocReg; }
543 bool isCoprocOption() const { return Kind == k_CoprocOption; }
544 bool isCondCode() const { return Kind == k_CondCode; }
545 bool isCCOut() const { return Kind == k_CCOut; }
546 bool isITMask() const { return Kind == k_ITCondMask; }
547 bool isITCondCode() const { return Kind == k_CondCode; }
548 bool isImm() const { return Kind == k_Immediate; }
549 bool isFPImm() const {
550 if (!isImm()) return false;
551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
552 if (!CE) return false;
553 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
556 bool isFBits16() const {
557 if (!isImm()) return false;
558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
559 if (!CE) return false;
560 int64_t Value = CE->getValue();
561 return Value >= 0 && Value <= 16;
563 bool isFBits32() const {
564 if (!isImm()) return false;
565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
566 if (!CE) return false;
567 int64_t Value = CE->getValue();
568 return Value >= 1 && Value <= 32;
570 bool isImm8s4() const {
571 if (!isImm()) return false;
572 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
573 if (!CE) return false;
574 int64_t Value = CE->getValue();
575 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
577 bool isImm0_1020s4() const {
578 if (!isImm()) return false;
579 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
580 if (!CE) return false;
581 int64_t Value = CE->getValue();
582 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
584 bool isImm0_508s4() const {
585 if (!isImm()) return false;
586 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
587 if (!CE) return false;
588 int64_t Value = CE->getValue();
589 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
591 bool isImm0_508s4Neg() const {
592 if (!isImm()) return false;
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594 if (!CE) return false;
595 int64_t Value = -CE->getValue();
596 // explicitly exclude zero. we want that to use the normal 0_508 version.
597 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
599 bool isImm0_255() const {
600 if (!isImm()) return false;
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return Value >= 0 && Value < 256;
606 bool isImm0_4095() const {
607 if (!isImm()) return false;
608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return Value >= 0 && Value < 4096;
613 bool isImm0_4095Neg() const {
614 if (!isImm()) return false;
615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
616 if (!CE) return false;
617 int64_t Value = -CE->getValue();
618 return Value > 0 && Value < 4096;
620 bool isImm0_1() const {
621 if (!isImm()) return false;
622 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
623 if (!CE) return false;
624 int64_t Value = CE->getValue();
625 return Value >= 0 && Value < 2;
627 bool isImm0_3() const {
628 if (!isImm()) return false;
629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
630 if (!CE) return false;
631 int64_t Value = CE->getValue();
632 return Value >= 0 && Value < 4;
634 bool isImm0_7() const {
635 if (!isImm()) return false;
636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
637 if (!CE) return false;
638 int64_t Value = CE->getValue();
639 return Value >= 0 && Value < 8;
641 bool isImm0_15() const {
642 if (!isImm()) return false;
643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
644 if (!CE) return false;
645 int64_t Value = CE->getValue();
646 return Value >= 0 && Value < 16;
648 bool isImm0_31() const {
649 if (!isImm()) return false;
650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651 if (!CE) return false;
652 int64_t Value = CE->getValue();
653 return Value >= 0 && Value < 32;
655 bool isImm0_63() const {
656 if (!isImm()) return false;
657 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
658 if (!CE) return false;
659 int64_t Value = CE->getValue();
660 return Value >= 0 && Value < 64;
662 bool isImm8() const {
663 if (!isImm()) return false;
664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
665 if (!CE) return false;
666 int64_t Value = CE->getValue();
669 bool isImm16() const {
670 if (!isImm()) return false;
671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
672 if (!CE) return false;
673 int64_t Value = CE->getValue();
676 bool isImm32() const {
677 if (!isImm()) return false;
678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
679 if (!CE) return false;
680 int64_t Value = CE->getValue();
683 bool isShrImm8() const {
684 if (!isImm()) return false;
685 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
686 if (!CE) return false;
687 int64_t Value = CE->getValue();
688 return Value > 0 && Value <= 8;
690 bool isShrImm16() const {
691 if (!isImm()) return false;
692 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
693 if (!CE) return false;
694 int64_t Value = CE->getValue();
695 return Value > 0 && Value <= 16;
697 bool isShrImm32() const {
698 if (!isImm()) return false;
699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
700 if (!CE) return false;
701 int64_t Value = CE->getValue();
702 return Value > 0 && Value <= 32;
704 bool isShrImm64() const {
705 if (!isImm()) return false;
706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
707 if (!CE) return false;
708 int64_t Value = CE->getValue();
709 return Value > 0 && Value <= 64;
711 bool isImm1_7() const {
712 if (!isImm()) return false;
713 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
714 if (!CE) return false;
715 int64_t Value = CE->getValue();
716 return Value > 0 && Value < 8;
718 bool isImm1_15() const {
719 if (!isImm()) return false;
720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
721 if (!CE) return false;
722 int64_t Value = CE->getValue();
723 return Value > 0 && Value < 16;
725 bool isImm1_31() const {
726 if (!isImm()) return false;
727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
728 if (!CE) return false;
729 int64_t Value = CE->getValue();
730 return Value > 0 && Value < 32;
732 bool isImm1_16() const {
733 if (!isImm()) return false;
734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
735 if (!CE) return false;
736 int64_t Value = CE->getValue();
737 return Value > 0 && Value < 17;
739 bool isImm1_32() const {
740 if (!isImm()) return false;
741 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
742 if (!CE) return false;
743 int64_t Value = CE->getValue();
744 return Value > 0 && Value < 33;
746 bool isImm0_32() const {
747 if (!isImm()) return false;
748 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
749 if (!CE) return false;
750 int64_t Value = CE->getValue();
751 return Value >= 0 && Value < 33;
753 bool isImm0_65535() const {
754 if (!isImm()) return false;
755 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
756 if (!CE) return false;
757 int64_t Value = CE->getValue();
758 return Value >= 0 && Value < 65536;
760 bool isImm0_65535Expr() const {
761 if (!isImm()) return false;
762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
763 // If it's not a constant expression, it'll generate a fixup and be
765 if (!CE) return true;
766 int64_t Value = CE->getValue();
767 return Value >= 0 && Value < 65536;
769 bool isImm24bit() const {
770 if (!isImm()) return false;
771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return Value >= 0 && Value <= 0xffffff;
776 bool isImmThumbSR() const {
777 if (!isImm()) return false;
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
780 int64_t Value = CE->getValue();
781 return Value > 0 && Value < 33;
783 bool isPKHLSLImm() const {
784 if (!isImm()) return false;
785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786 if (!CE) return false;
787 int64_t Value = CE->getValue();
788 return Value >= 0 && Value < 32;
790 bool isPKHASRImm() const {
791 if (!isImm()) return false;
792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793 if (!CE) return false;
794 int64_t Value = CE->getValue();
795 return Value > 0 && Value <= 32;
797 bool isAdrLabel() const {
798 // If we have an immediate that's not a constant, treat it as a label
799 // reference needing a fixup. If it is a constant, but it can't fit
800 // into shift immediate encoding, we reject it.
801 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
802 else return (isARMSOImm() || isARMSOImmNeg());
804 bool isARMSOImm() const {
805 if (!isImm()) return false;
806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 if (!CE) return false;
808 int64_t Value = CE->getValue();
809 return ARM_AM::getSOImmVal(Value) != -1;
811 bool isARMSOImmNot() const {
812 if (!isImm()) return false;
813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814 if (!CE) return false;
815 int64_t Value = CE->getValue();
816 return ARM_AM::getSOImmVal(~Value) != -1;
818 bool isARMSOImmNeg() const {
819 if (!isImm()) return false;
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Value = CE->getValue();
823 // Only use this when not representable as a plain so_imm.
824 return ARM_AM::getSOImmVal(Value) == -1 &&
825 ARM_AM::getSOImmVal(-Value) != -1;
827 bool isT2SOImm() const {
828 if (!isImm()) return false;
829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
830 if (!CE) return false;
831 int64_t Value = CE->getValue();
832 return ARM_AM::getT2SOImmVal(Value) != -1;
834 bool isT2SOImmNot() const {
835 if (!isImm()) return false;
836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
837 if (!CE) return false;
838 int64_t Value = CE->getValue();
839 return ARM_AM::getT2SOImmVal(~Value) != -1;
841 bool isT2SOImmNeg() const {
842 if (!isImm()) return false;
843 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
844 if (!CE) return false;
845 int64_t Value = CE->getValue();
846 // Only use this when not representable as a plain so_imm.
847 return ARM_AM::getT2SOImmVal(Value) == -1 &&
848 ARM_AM::getT2SOImmVal(-Value) != -1;
850 bool isSetEndImm() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value == 1 || Value == 0;
857 bool isReg() const { return Kind == k_Register; }
858 bool isRegList() const { return Kind == k_RegisterList; }
859 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
860 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
861 bool isToken() const { return Kind == k_Token; }
862 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
863 bool isMem() const { return Kind == k_Memory; }
864 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
865 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
866 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
867 bool isRotImm() const { return Kind == k_RotateImmediate; }
868 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
869 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
870 bool isPostIdxReg() const {
871 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
873 bool isMemNoOffset(bool alignOK = false) const {
876 // No offset of any kind.
877 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
878 (alignOK || Memory.Alignment == 0);
880 bool isMemPCRelImm12() const {
881 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
883 // Base register must be PC.
884 if (Memory.BaseRegNum != ARM::PC)
886 // Immediate offset in range [-4095, 4095].
887 if (!Memory.OffsetImm) return true;
888 int64_t Val = Memory.OffsetImm->getValue();
889 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
891 bool isAlignedMemory() const {
892 return isMemNoOffset(true);
894 bool isAddrMode2() const {
895 if (!isMem() || Memory.Alignment != 0) return false;
896 // Check for register offset.
897 if (Memory.OffsetRegNum) return true;
898 // Immediate offset in range [-4095, 4095].
899 if (!Memory.OffsetImm) return true;
900 int64_t Val = Memory.OffsetImm->getValue();
901 return Val > -4096 && Val < 4096;
903 bool isAM2OffsetImm() const {
904 if (!isImm()) return false;
905 // Immediate offset in range [-4095, 4095].
906 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
907 if (!CE) return false;
908 int64_t Val = CE->getValue();
909 return Val > -4096 && Val < 4096;
911 bool isAddrMode3() const {
912 // If we have an immediate that's not a constant, treat it as a label
913 // reference needing a fixup. If it is a constant, it's something else
915 if (isImm() && !isa<MCConstantExpr>(getImm()))
917 if (!isMem() || Memory.Alignment != 0) return false;
918 // No shifts are legal for AM3.
919 if (Memory.ShiftType != ARM_AM::no_shift) return false;
920 // Check for register offset.
921 if (Memory.OffsetRegNum) return true;
922 // Immediate offset in range [-255, 255].
923 if (!Memory.OffsetImm) return true;
924 int64_t Val = Memory.OffsetImm->getValue();
925 // The #-0 offset is encoded as INT32_MIN, and we have to check
927 return (Val > -256 && Val < 256) || Val == INT32_MIN;
929 bool isAM3Offset() const {
930 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
932 if (Kind == k_PostIndexRegister)
933 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
934 // Immediate offset in range [-255, 255].
935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936 if (!CE) return false;
937 int64_t Val = CE->getValue();
938 // Special case, #-0 is INT32_MIN.
939 return (Val > -256 && Val < 256) || Val == INT32_MIN;
941 bool isAddrMode5() const {
942 // If we have an immediate that's not a constant, treat it as a label
943 // reference needing a fixup. If it is a constant, it's something else
945 if (isImm() && !isa<MCConstantExpr>(getImm()))
947 if (!isMem() || Memory.Alignment != 0) return false;
948 // Check for register offset.
949 if (Memory.OffsetRegNum) return false;
950 // Immediate offset in range [-1020, 1020] and a multiple of 4.
951 if (!Memory.OffsetImm) return true;
952 int64_t Val = Memory.OffsetImm->getValue();
953 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
956 bool isMemTBB() const {
957 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
958 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
962 bool isMemTBH() const {
963 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
964 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
965 Memory.Alignment != 0 )
969 bool isMemRegOffset() const {
970 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
974 bool isT2MemRegOffset() const {
975 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
976 Memory.Alignment != 0)
978 // Only lsl #{0, 1, 2, 3} allowed.
979 if (Memory.ShiftType == ARM_AM::no_shift)
981 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
985 bool isMemThumbRR() const {
986 // Thumb reg+reg addressing is simple. Just two registers, a base and
987 // an offset. No shifts, negations or any other complicating factors.
988 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
989 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
991 return isARMLowRegister(Memory.BaseRegNum) &&
992 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
994 bool isMemThumbRIs4() const {
995 if (!isMem() || Memory.OffsetRegNum != 0 ||
996 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
998 // Immediate offset, multiple of 4 in range [0, 124].
999 if (!Memory.OffsetImm) return true;
1000 int64_t Val = Memory.OffsetImm->getValue();
1001 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1003 bool isMemThumbRIs2() const {
1004 if (!isMem() || Memory.OffsetRegNum != 0 ||
1005 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1007 // Immediate offset, multiple of 4 in range [0, 62].
1008 if (!Memory.OffsetImm) return true;
1009 int64_t Val = Memory.OffsetImm->getValue();
1010 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1012 bool isMemThumbRIs1() const {
1013 if (!isMem() || Memory.OffsetRegNum != 0 ||
1014 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1016 // Immediate offset in range [0, 31].
1017 if (!Memory.OffsetImm) return true;
1018 int64_t Val = Memory.OffsetImm->getValue();
1019 return Val >= 0 && Val <= 31;
1021 bool isMemThumbSPI() const {
1022 if (!isMem() || Memory.OffsetRegNum != 0 ||
1023 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1025 // Immediate offset, multiple of 4 in range [0, 1020].
1026 if (!Memory.OffsetImm) return true;
1027 int64_t Val = Memory.OffsetImm->getValue();
1028 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1030 bool isMemImm8s4Offset() const {
1031 // If we have an immediate that's not a constant, treat it as a label
1032 // reference needing a fixup. If it is a constant, it's something else
1033 // and we reject it.
1034 if (isImm() && !isa<MCConstantExpr>(getImm()))
1036 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1038 // Immediate offset a multiple of 4 in range [-1020, 1020].
1039 if (!Memory.OffsetImm) return true;
1040 int64_t Val = Memory.OffsetImm->getValue();
1041 // Special case, #-0 is INT32_MIN.
1042 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1044 bool isMemImm0_1020s4Offset() const {
1045 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1047 // Immediate offset a multiple of 4 in range [0, 1020].
1048 if (!Memory.OffsetImm) return true;
1049 int64_t Val = Memory.OffsetImm->getValue();
1050 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1052 bool isMemImm8Offset() const {
1053 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1055 // Base reg of PC isn't allowed for these encodings.
1056 if (Memory.BaseRegNum == ARM::PC) return false;
1057 // Immediate offset in range [-255, 255].
1058 if (!Memory.OffsetImm) return true;
1059 int64_t Val = Memory.OffsetImm->getValue();
1060 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1062 bool isMemPosImm8Offset() const {
1063 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1065 // Immediate offset in range [0, 255].
1066 if (!Memory.OffsetImm) return true;
1067 int64_t Val = Memory.OffsetImm->getValue();
1068 return Val >= 0 && Val < 256;
1070 bool isMemNegImm8Offset() const {
1071 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1073 // Base reg of PC isn't allowed for these encodings.
1074 if (Memory.BaseRegNum == ARM::PC) return false;
1075 // Immediate offset in range [-255, -1].
1076 if (!Memory.OffsetImm) return false;
1077 int64_t Val = Memory.OffsetImm->getValue();
1078 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1080 bool isMemUImm12Offset() const {
1081 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1083 // Immediate offset in range [0, 4095].
1084 if (!Memory.OffsetImm) return true;
1085 int64_t Val = Memory.OffsetImm->getValue();
1086 return (Val >= 0 && Val < 4096);
1088 bool isMemImm12Offset() const {
1089 // If we have an immediate that's not a constant, treat it as a label
1090 // reference needing a fixup. If it is a constant, it's something else
1091 // and we reject it.
1092 if (isImm() && !isa<MCConstantExpr>(getImm()))
1095 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1097 // Immediate offset in range [-4095, 4095].
1098 if (!Memory.OffsetImm) return true;
1099 int64_t Val = Memory.OffsetImm->getValue();
1100 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1102 bool isPostIdxImm8() const {
1103 if (!isImm()) return false;
1104 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1105 if (!CE) return false;
1106 int64_t Val = CE->getValue();
1107 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1109 bool isPostIdxImm8s4() const {
1110 if (!isImm()) return false;
1111 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1112 if (!CE) return false;
1113 int64_t Val = CE->getValue();
1114 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1118 bool isMSRMask() const { return Kind == k_MSRMask; }
1119 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1122 bool isSingleSpacedVectorList() const {
1123 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1125 bool isDoubleSpacedVectorList() const {
1126 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1128 bool isVecListOneD() const {
1129 if (!isSingleSpacedVectorList()) return false;
1130 return VectorList.Count == 1;
1133 bool isVecListDPair() const {
1134 if (!isSingleSpacedVectorList()) return false;
1135 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1136 .contains(VectorList.RegNum));
1139 bool isVecListThreeD() const {
1140 if (!isSingleSpacedVectorList()) return false;
1141 return VectorList.Count == 3;
1144 bool isVecListFourD() const {
1145 if (!isSingleSpacedVectorList()) return false;
1146 return VectorList.Count == 4;
1149 bool isVecListDPairSpaced() const {
1150 if (isSingleSpacedVectorList()) return false;
1151 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1152 .contains(VectorList.RegNum));
1155 bool isVecListThreeQ() const {
1156 if (!isDoubleSpacedVectorList()) return false;
1157 return VectorList.Count == 3;
1160 bool isVecListFourQ() const {
1161 if (!isDoubleSpacedVectorList()) return false;
1162 return VectorList.Count == 4;
1165 bool isSingleSpacedVectorAllLanes() const {
1166 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1168 bool isDoubleSpacedVectorAllLanes() const {
1169 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1171 bool isVecListOneDAllLanes() const {
1172 if (!isSingleSpacedVectorAllLanes()) return false;
1173 return VectorList.Count == 1;
1176 bool isVecListDPairAllLanes() const {
1177 if (!isSingleSpacedVectorAllLanes()) return false;
1178 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1179 .contains(VectorList.RegNum));
1182 bool isVecListDPairSpacedAllLanes() const {
1183 if (!isDoubleSpacedVectorAllLanes()) return false;
1184 return VectorList.Count == 2;
1187 bool isVecListThreeDAllLanes() const {
1188 if (!isSingleSpacedVectorAllLanes()) return false;
1189 return VectorList.Count == 3;
1192 bool isVecListThreeQAllLanes() const {
1193 if (!isDoubleSpacedVectorAllLanes()) return false;
1194 return VectorList.Count == 3;
1197 bool isVecListFourDAllLanes() const {
1198 if (!isSingleSpacedVectorAllLanes()) return false;
1199 return VectorList.Count == 4;
1202 bool isVecListFourQAllLanes() const {
1203 if (!isDoubleSpacedVectorAllLanes()) return false;
1204 return VectorList.Count == 4;
1207 bool isSingleSpacedVectorIndexed() const {
1208 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1210 bool isDoubleSpacedVectorIndexed() const {
1211 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1213 bool isVecListOneDByteIndexed() const {
1214 if (!isSingleSpacedVectorIndexed()) return false;
1215 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1218 bool isVecListOneDHWordIndexed() const {
1219 if (!isSingleSpacedVectorIndexed()) return false;
1220 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1223 bool isVecListOneDWordIndexed() const {
1224 if (!isSingleSpacedVectorIndexed()) return false;
1225 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1228 bool isVecListTwoDByteIndexed() const {
1229 if (!isSingleSpacedVectorIndexed()) return false;
1230 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1233 bool isVecListTwoDHWordIndexed() const {
1234 if (!isSingleSpacedVectorIndexed()) return false;
1235 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1238 bool isVecListTwoQWordIndexed() const {
1239 if (!isDoubleSpacedVectorIndexed()) return false;
1240 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1243 bool isVecListTwoQHWordIndexed() const {
1244 if (!isDoubleSpacedVectorIndexed()) return false;
1245 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1248 bool isVecListTwoDWordIndexed() const {
1249 if (!isSingleSpacedVectorIndexed()) return false;
1250 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1253 bool isVecListThreeDByteIndexed() const {
1254 if (!isSingleSpacedVectorIndexed()) return false;
1255 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1258 bool isVecListThreeDHWordIndexed() const {
1259 if (!isSingleSpacedVectorIndexed()) return false;
1260 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1263 bool isVecListThreeQWordIndexed() const {
1264 if (!isDoubleSpacedVectorIndexed()) return false;
1265 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1268 bool isVecListThreeQHWordIndexed() const {
1269 if (!isDoubleSpacedVectorIndexed()) return false;
1270 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1273 bool isVecListThreeDWordIndexed() const {
1274 if (!isSingleSpacedVectorIndexed()) return false;
1275 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1278 bool isVecListFourDByteIndexed() const {
1279 if (!isSingleSpacedVectorIndexed()) return false;
1280 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1283 bool isVecListFourDHWordIndexed() const {
1284 if (!isSingleSpacedVectorIndexed()) return false;
1285 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1288 bool isVecListFourQWordIndexed() const {
1289 if (!isDoubleSpacedVectorIndexed()) return false;
1290 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1293 bool isVecListFourQHWordIndexed() const {
1294 if (!isDoubleSpacedVectorIndexed()) return false;
1295 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1298 bool isVecListFourDWordIndexed() const {
1299 if (!isSingleSpacedVectorIndexed()) return false;
1300 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1303 bool isVectorIndex8() const {
1304 if (Kind != k_VectorIndex) return false;
1305 return VectorIndex.Val < 8;
1307 bool isVectorIndex16() const {
1308 if (Kind != k_VectorIndex) return false;
1309 return VectorIndex.Val < 4;
1311 bool isVectorIndex32() const {
1312 if (Kind != k_VectorIndex) return false;
1313 return VectorIndex.Val < 2;
1316 bool isNEONi8splat() const {
1317 if (!isImm()) return false;
1318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1319 // Must be a constant.
1320 if (!CE) return false;
1321 int64_t Value = CE->getValue();
1322 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1324 return Value >= 0 && Value < 256;
1327 bool isNEONi16splat() const {
1328 if (!isImm()) return false;
1329 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1330 // Must be a constant.
1331 if (!CE) return false;
1332 int64_t Value = CE->getValue();
1333 // i16 value in the range [0,255] or [0x0100, 0xff00]
1334 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1337 bool isNEONi32splat() const {
1338 if (!isImm()) return false;
1339 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1340 // Must be a constant.
1341 if (!CE) return false;
1342 int64_t Value = CE->getValue();
1343 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1344 return (Value >= 0 && Value < 256) ||
1345 (Value >= 0x0100 && Value <= 0xff00) ||
1346 (Value >= 0x010000 && Value <= 0xff0000) ||
1347 (Value >= 0x01000000 && Value <= 0xff000000);
1350 bool isNEONi32vmov() const {
1351 if (!isImm()) return false;
1352 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1353 // Must be a constant.
1354 if (!CE) return false;
1355 int64_t Value = CE->getValue();
1356 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1357 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1358 return (Value >= 0 && Value < 256) ||
1359 (Value >= 0x0100 && Value <= 0xff00) ||
1360 (Value >= 0x010000 && Value <= 0xff0000) ||
1361 (Value >= 0x01000000 && Value <= 0xff000000) ||
1362 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1363 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1365 bool isNEONi32vmovNeg() const {
1366 if (!isImm()) return false;
1367 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1368 // Must be a constant.
1369 if (!CE) return false;
1370 int64_t Value = ~CE->getValue();
1371 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1372 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1373 return (Value >= 0 && Value < 256) ||
1374 (Value >= 0x0100 && Value <= 0xff00) ||
1375 (Value >= 0x010000 && Value <= 0xff0000) ||
1376 (Value >= 0x01000000 && Value <= 0xff000000) ||
1377 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1378 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1381 bool isNEONi64splat() const {
1382 if (!isImm()) return false;
1383 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1384 // Must be a constant.
1385 if (!CE) return false;
1386 uint64_t Value = CE->getValue();
1387 // i64 value with each byte being either 0 or 0xff.
1388 for (unsigned i = 0; i < 8; ++i)
1389 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1393 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1394 // Add as immediates when possible. Null MCExpr = 0.
1396 Inst.addOperand(MCOperand::CreateImm(0));
1397 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1398 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1400 Inst.addOperand(MCOperand::CreateExpr(Expr));
1403 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1404 assert(N == 2 && "Invalid number of operands!");
1405 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1406 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1407 Inst.addOperand(MCOperand::CreateReg(RegNum));
1410 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1411 assert(N == 1 && "Invalid number of operands!");
1412 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1415 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1416 assert(N == 1 && "Invalid number of operands!");
1417 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1420 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1421 assert(N == 1 && "Invalid number of operands!");
1422 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1425 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1426 assert(N == 1 && "Invalid number of operands!");
1427 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1430 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1431 assert(N == 1 && "Invalid number of operands!");
1432 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1435 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1436 assert(N == 1 && "Invalid number of operands!");
1437 Inst.addOperand(MCOperand::CreateReg(getReg()));
1440 void addRegOperands(MCInst &Inst, unsigned N) const {
1441 assert(N == 1 && "Invalid number of operands!");
1442 Inst.addOperand(MCOperand::CreateReg(getReg()));
1445 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1446 assert(N == 3 && "Invalid number of operands!");
1447 assert(isRegShiftedReg() &&
1448 "addRegShiftedRegOperands() on non RegShiftedReg!");
1449 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1450 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1451 Inst.addOperand(MCOperand::CreateImm(
1452 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1455 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1456 assert(N == 2 && "Invalid number of operands!");
1457 assert(isRegShiftedImm() &&
1458 "addRegShiftedImmOperands() on non RegShiftedImm!");
1459 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1460 // Shift of #32 is encoded as 0 where permitted
1461 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1462 Inst.addOperand(MCOperand::CreateImm(
1463 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1466 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1467 assert(N == 1 && "Invalid number of operands!");
1468 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1472 void addRegListOperands(MCInst &Inst, unsigned N) const {
1473 assert(N == 1 && "Invalid number of operands!");
1474 const SmallVectorImpl<unsigned> &RegList = getRegList();
1475 for (SmallVectorImpl<unsigned>::const_iterator
1476 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1477 Inst.addOperand(MCOperand::CreateReg(*I));
1480 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1481 addRegListOperands(Inst, N);
1484 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1485 addRegListOperands(Inst, N);
1488 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1489 assert(N == 1 && "Invalid number of operands!");
1490 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1491 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1494 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1495 assert(N == 1 && "Invalid number of operands!");
1496 // Munge the lsb/width into a bitfield mask.
1497 unsigned lsb = Bitfield.LSB;
1498 unsigned width = Bitfield.Width;
1499 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1500 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1501 (32 - (lsb + width)));
1502 Inst.addOperand(MCOperand::CreateImm(Mask));
1505 void addImmOperands(MCInst &Inst, unsigned N) const {
1506 assert(N == 1 && "Invalid number of operands!");
1507 addExpr(Inst, getImm());
1510 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1511 assert(N == 1 && "Invalid number of operands!");
1512 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1513 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1516 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1517 assert(N == 1 && "Invalid number of operands!");
1518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1519 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1522 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1523 assert(N == 1 && "Invalid number of operands!");
1524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1525 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1526 Inst.addOperand(MCOperand::CreateImm(Val));
1529 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1530 assert(N == 1 && "Invalid number of operands!");
1531 // FIXME: We really want to scale the value here, but the LDRD/STRD
1532 // instruction don't encode operands that way yet.
1533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1534 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1537 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1538 assert(N == 1 && "Invalid number of operands!");
1539 // The immediate is scaled by four in the encoding and is stored
1540 // in the MCInst as such. Lop off the low two bits here.
1541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1542 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1545 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1546 assert(N == 1 && "Invalid number of operands!");
1547 // The immediate is scaled by four in the encoding and is stored
1548 // in the MCInst as such. Lop off the low two bits here.
1549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1550 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1553 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1554 assert(N == 1 && "Invalid number of operands!");
1555 // The immediate is scaled by four in the encoding and is stored
1556 // in the MCInst as such. Lop off the low two bits here.
1557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1558 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1561 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1562 assert(N == 1 && "Invalid number of operands!");
1563 // The constant encodes as the immediate-1, and we store in the instruction
1564 // the bits as encoded, so subtract off one here.
1565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1566 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1569 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1570 assert(N == 1 && "Invalid number of operands!");
1571 // The constant encodes as the immediate-1, and we store in the instruction
1572 // the bits as encoded, so subtract off one here.
1573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1574 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1577 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1578 assert(N == 1 && "Invalid number of operands!");
1579 // The constant encodes as the immediate, except for 32, which encodes as
1581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1582 unsigned Imm = CE->getValue();
1583 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1586 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1587 assert(N == 1 && "Invalid number of operands!");
1588 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1589 // the instruction as well.
1590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1591 int Val = CE->getValue();
1592 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1595 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1596 assert(N == 1 && "Invalid number of operands!");
1597 // The operand is actually a t2_so_imm, but we have its bitwise
1598 // negation in the assembly source, so twiddle it here.
1599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1600 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1603 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1604 assert(N == 1 && "Invalid number of operands!");
1605 // The operand is actually a t2_so_imm, but we have its
1606 // negation in the assembly source, so twiddle it here.
1607 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1608 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1611 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1612 assert(N == 1 && "Invalid number of operands!");
1613 // The operand is actually an imm0_4095, but we have its
1614 // negation in the assembly source, so twiddle it here.
1615 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1616 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1619 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1620 assert(N == 1 && "Invalid number of operands!");
1621 // The operand is actually a so_imm, but we have its bitwise
1622 // negation in the assembly source, so twiddle it here.
1623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1627 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1628 assert(N == 1 && "Invalid number of operands!");
1629 // The operand is actually a so_imm, but we have its
1630 // negation in the assembly source, so twiddle it here.
1631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1632 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1635 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1636 assert(N == 1 && "Invalid number of operands!");
1637 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1640 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1641 assert(N == 1 && "Invalid number of operands!");
1642 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1645 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1646 assert(N == 1 && "Invalid number of operands!");
1647 int32_t Imm = Memory.OffsetImm->getValue();
1648 // FIXME: Handle #-0
1649 if (Imm == INT32_MIN) Imm = 0;
1650 Inst.addOperand(MCOperand::CreateImm(Imm));
1653 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1654 assert(N == 1 && "Invalid number of operands!");
1655 assert(isImm() && "Not an immediate!");
1657 // If we have an immediate that's not a constant, treat it as a label
1658 // reference needing a fixup.
1659 if (!isa<MCConstantExpr>(getImm())) {
1660 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1664 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1665 int Val = CE->getValue();
1666 Inst.addOperand(MCOperand::CreateImm(Val));
1669 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1670 assert(N == 2 && "Invalid number of operands!");
1671 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1672 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1675 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1676 assert(N == 3 && "Invalid number of operands!");
1677 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1678 if (!Memory.OffsetRegNum) {
1679 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1680 // Special case for #-0
1681 if (Val == INT32_MIN) Val = 0;
1682 if (Val < 0) Val = -Val;
1683 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1685 // For register offset, we encode the shift type and negation flag
1687 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1688 Memory.ShiftImm, Memory.ShiftType);
1690 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1691 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1692 Inst.addOperand(MCOperand::CreateImm(Val));
1695 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1696 assert(N == 2 && "Invalid number of operands!");
1697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1698 assert(CE && "non-constant AM2OffsetImm operand!");
1699 int32_t Val = CE->getValue();
1700 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1701 // Special case for #-0
1702 if (Val == INT32_MIN) Val = 0;
1703 if (Val < 0) Val = -Val;
1704 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1705 Inst.addOperand(MCOperand::CreateReg(0));
1706 Inst.addOperand(MCOperand::CreateImm(Val));
1709 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1710 assert(N == 3 && "Invalid number of operands!");
1711 // If we have an immediate that's not a constant, treat it as a label
1712 // reference needing a fixup. If it is a constant, it's something else
1713 // and we reject it.
1715 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1716 Inst.addOperand(MCOperand::CreateReg(0));
1717 Inst.addOperand(MCOperand::CreateImm(0));
1721 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1722 if (!Memory.OffsetRegNum) {
1723 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1724 // Special case for #-0
1725 if (Val == INT32_MIN) Val = 0;
1726 if (Val < 0) Val = -Val;
1727 Val = ARM_AM::getAM3Opc(AddSub, Val);
1729 // For register offset, we encode the shift type and negation flag
1731 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1733 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1734 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1735 Inst.addOperand(MCOperand::CreateImm(Val));
1738 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1739 assert(N == 2 && "Invalid number of operands!");
1740 if (Kind == k_PostIndexRegister) {
1742 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1743 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1744 Inst.addOperand(MCOperand::CreateImm(Val));
1749 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1750 int32_t Val = CE->getValue();
1751 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1752 // Special case for #-0
1753 if (Val == INT32_MIN) Val = 0;
1754 if (Val < 0) Val = -Val;
1755 Val = ARM_AM::getAM3Opc(AddSub, Val);
1756 Inst.addOperand(MCOperand::CreateReg(0));
1757 Inst.addOperand(MCOperand::CreateImm(Val));
1760 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1761 assert(N == 2 && "Invalid number of operands!");
1762 // If we have an immediate that's not a constant, treat it as a label
1763 // reference needing a fixup. If it is a constant, it's something else
1764 // and we reject it.
1766 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1767 Inst.addOperand(MCOperand::CreateImm(0));
1771 // The lower two bits are always zero and as such are not encoded.
1772 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1773 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1774 // Special case for #-0
1775 if (Val == INT32_MIN) Val = 0;
1776 if (Val < 0) Val = -Val;
1777 Val = ARM_AM::getAM5Opc(AddSub, Val);
1778 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1779 Inst.addOperand(MCOperand::CreateImm(Val));
1782 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1783 assert(N == 2 && "Invalid number of operands!");
1784 // If we have an immediate that's not a constant, treat it as a label
1785 // reference needing a fixup. If it is a constant, it's something else
1786 // and we reject it.
1788 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1789 Inst.addOperand(MCOperand::CreateImm(0));
1793 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1794 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1795 Inst.addOperand(MCOperand::CreateImm(Val));
1798 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1799 assert(N == 2 && "Invalid number of operands!");
1800 // The lower two bits are always zero and as such are not encoded.
1801 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1802 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1803 Inst.addOperand(MCOperand::CreateImm(Val));
1806 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1807 assert(N == 2 && "Invalid number of operands!");
1808 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1809 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1810 Inst.addOperand(MCOperand::CreateImm(Val));
1813 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1814 addMemImm8OffsetOperands(Inst, N);
1817 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1818 addMemImm8OffsetOperands(Inst, N);
1821 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1822 assert(N == 2 && "Invalid number of operands!");
1823 // If this is an immediate, it's a label reference.
1825 addExpr(Inst, getImm());
1826 Inst.addOperand(MCOperand::CreateImm(0));
1830 // Otherwise, it's a normal memory reg+offset.
1831 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1832 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1833 Inst.addOperand(MCOperand::CreateImm(Val));
1836 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1837 assert(N == 2 && "Invalid number of operands!");
1838 // If this is an immediate, it's a label reference.
1840 addExpr(Inst, getImm());
1841 Inst.addOperand(MCOperand::CreateImm(0));
1845 // Otherwise, it's a normal memory reg+offset.
1846 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1847 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1848 Inst.addOperand(MCOperand::CreateImm(Val));
1851 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1852 assert(N == 2 && "Invalid number of operands!");
1853 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1854 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1857 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1858 assert(N == 2 && "Invalid number of operands!");
1859 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1860 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1863 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 3 && "Invalid number of operands!");
1866 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1867 Memory.ShiftImm, Memory.ShiftType);
1868 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1869 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1870 Inst.addOperand(MCOperand::CreateImm(Val));
1873 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1874 assert(N == 3 && "Invalid number of operands!");
1875 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1876 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1877 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1880 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1881 assert(N == 2 && "Invalid number of operands!");
1882 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1883 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1886 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1887 assert(N == 2 && "Invalid number of operands!");
1888 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1889 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1890 Inst.addOperand(MCOperand::CreateImm(Val));
1893 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1894 assert(N == 2 && "Invalid number of operands!");
1895 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1896 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1897 Inst.addOperand(MCOperand::CreateImm(Val));
1900 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1901 assert(N == 2 && "Invalid number of operands!");
1902 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1903 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1904 Inst.addOperand(MCOperand::CreateImm(Val));
1907 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1908 assert(N == 2 && "Invalid number of operands!");
1909 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1910 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1911 Inst.addOperand(MCOperand::CreateImm(Val));
1914 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1915 assert(N == 1 && "Invalid number of operands!");
1916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1917 assert(CE && "non-constant post-idx-imm8 operand!");
1918 int Imm = CE->getValue();
1919 bool isAdd = Imm >= 0;
1920 if (Imm == INT32_MIN) Imm = 0;
1921 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1922 Inst.addOperand(MCOperand::CreateImm(Imm));
1925 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1926 assert(N == 1 && "Invalid number of operands!");
1927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1928 assert(CE && "non-constant post-idx-imm8s4 operand!");
1929 int Imm = CE->getValue();
1930 bool isAdd = Imm >= 0;
1931 if (Imm == INT32_MIN) Imm = 0;
1932 // Immediate is scaled by 4.
1933 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1934 Inst.addOperand(MCOperand::CreateImm(Imm));
1937 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1938 assert(N == 2 && "Invalid number of operands!");
1939 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1940 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1943 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1944 assert(N == 2 && "Invalid number of operands!");
1945 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1946 // The sign, shift type, and shift amount are encoded in a single operand
1947 // using the AM2 encoding helpers.
1948 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1949 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1950 PostIdxReg.ShiftTy);
1951 Inst.addOperand(MCOperand::CreateImm(Imm));
1954 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1955 assert(N == 1 && "Invalid number of operands!");
1956 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1959 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1960 assert(N == 1 && "Invalid number of operands!");
1961 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1964 void addVecListOperands(MCInst &Inst, unsigned N) const {
1965 assert(N == 1 && "Invalid number of operands!");
1966 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1969 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1970 assert(N == 2 && "Invalid number of operands!");
1971 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1972 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1975 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1976 assert(N == 1 && "Invalid number of operands!");
1977 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1980 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1981 assert(N == 1 && "Invalid number of operands!");
1982 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1985 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1986 assert(N == 1 && "Invalid number of operands!");
1987 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1990 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1991 assert(N == 1 && "Invalid number of operands!");
1992 // The immediate encodes the type of constant as well as the value.
1993 // Mask in that this is an i8 splat.
1994 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1995 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1998 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1999 assert(N == 1 && "Invalid number of operands!");
2000 // The immediate encodes the type of constant as well as the value.
2001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2002 unsigned Value = CE->getValue();
2004 Value = (Value >> 8) | 0xa00;
2007 Inst.addOperand(MCOperand::CreateImm(Value));
2010 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2011 assert(N == 1 && "Invalid number of operands!");
2012 // The immediate encodes the type of constant as well as the value.
2013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2014 unsigned Value = CE->getValue();
2015 if (Value >= 256 && Value <= 0xff00)
2016 Value = (Value >> 8) | 0x200;
2017 else if (Value > 0xffff && Value <= 0xff0000)
2018 Value = (Value >> 16) | 0x400;
2019 else if (Value > 0xffffff)
2020 Value = (Value >> 24) | 0x600;
2021 Inst.addOperand(MCOperand::CreateImm(Value));
2024 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2025 assert(N == 1 && "Invalid number of operands!");
2026 // The immediate encodes the type of constant as well as the value.
2027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2028 unsigned Value = CE->getValue();
2029 if (Value >= 256 && Value <= 0xffff)
2030 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2031 else if (Value > 0xffff && Value <= 0xffffff)
2032 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2033 else if (Value > 0xffffff)
2034 Value = (Value >> 24) | 0x600;
2035 Inst.addOperand(MCOperand::CreateImm(Value));
2038 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2039 assert(N == 1 && "Invalid number of operands!");
2040 // The immediate encodes the type of constant as well as the value.
2041 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2042 unsigned Value = ~CE->getValue();
2043 if (Value >= 256 && Value <= 0xffff)
2044 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2045 else if (Value > 0xffff && Value <= 0xffffff)
2046 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2047 else if (Value > 0xffffff)
2048 Value = (Value >> 24) | 0x600;
2049 Inst.addOperand(MCOperand::CreateImm(Value));
2052 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2053 assert(N == 1 && "Invalid number of operands!");
2054 // The immediate encodes the type of constant as well as the value.
2055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2056 uint64_t Value = CE->getValue();
2058 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2059 Imm |= (Value & 1) << i;
2061 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2064 virtual void print(raw_ostream &OS) const;
2066 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2067 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2068 Op->ITMask.Mask = Mask;
2074 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2075 ARMOperand *Op = new ARMOperand(k_CondCode);
2082 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2083 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2084 Op->Cop.Val = CopVal;
2090 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2091 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2092 Op->Cop.Val = CopVal;
2098 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2099 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2106 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2107 ARMOperand *Op = new ARMOperand(k_CCOut);
2108 Op->Reg.RegNum = RegNum;
2114 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2115 ARMOperand *Op = new ARMOperand(k_Token);
2116 Op->Tok.Data = Str.data();
2117 Op->Tok.Length = Str.size();
2123 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2124 ARMOperand *Op = new ARMOperand(k_Register);
2125 Op->Reg.RegNum = RegNum;
2131 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2136 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2137 Op->RegShiftedReg.ShiftTy = ShTy;
2138 Op->RegShiftedReg.SrcReg = SrcReg;
2139 Op->RegShiftedReg.ShiftReg = ShiftReg;
2140 Op->RegShiftedReg.ShiftImm = ShiftImm;
2146 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2150 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2151 Op->RegShiftedImm.ShiftTy = ShTy;
2152 Op->RegShiftedImm.SrcReg = SrcReg;
2153 Op->RegShiftedImm.ShiftImm = ShiftImm;
2159 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2161 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2162 Op->ShifterImm.isASR = isASR;
2163 Op->ShifterImm.Imm = Imm;
2169 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2170 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2171 Op->RotImm.Imm = Imm;
2177 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2179 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2180 Op->Bitfield.LSB = LSB;
2181 Op->Bitfield.Width = Width;
2188 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2189 SMLoc StartLoc, SMLoc EndLoc) {
2190 KindTy Kind = k_RegisterList;
2192 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2193 Kind = k_DPRRegisterList;
2194 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2195 contains(Regs.front().first))
2196 Kind = k_SPRRegisterList;
2198 ARMOperand *Op = new ARMOperand(Kind);
2199 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2200 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2201 Op->Registers.push_back(I->first);
2202 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2203 Op->StartLoc = StartLoc;
2204 Op->EndLoc = EndLoc;
2208 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2209 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2210 ARMOperand *Op = new ARMOperand(k_VectorList);
2211 Op->VectorList.RegNum = RegNum;
2212 Op->VectorList.Count = Count;
2213 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2219 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2220 bool isDoubleSpaced,
2222 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2223 Op->VectorList.RegNum = RegNum;
2224 Op->VectorList.Count = Count;
2225 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2231 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2233 bool isDoubleSpaced,
2235 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2236 Op->VectorList.RegNum = RegNum;
2237 Op->VectorList.Count = Count;
2238 Op->VectorList.LaneIndex = Index;
2239 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2245 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2247 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2248 Op->VectorIndex.Val = Idx;
2254 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2255 ARMOperand *Op = new ARMOperand(k_Immediate);
2262 static ARMOperand *CreateMem(unsigned BaseRegNum,
2263 const MCConstantExpr *OffsetImm,
2264 unsigned OffsetRegNum,
2265 ARM_AM::ShiftOpc ShiftType,
2270 ARMOperand *Op = new ARMOperand(k_Memory);
2271 Op->Memory.BaseRegNum = BaseRegNum;
2272 Op->Memory.OffsetImm = OffsetImm;
2273 Op->Memory.OffsetRegNum = OffsetRegNum;
2274 Op->Memory.ShiftType = ShiftType;
2275 Op->Memory.ShiftImm = ShiftImm;
2276 Op->Memory.Alignment = Alignment;
2277 Op->Memory.isNegative = isNegative;
2283 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2284 ARM_AM::ShiftOpc ShiftTy,
2287 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2288 Op->PostIdxReg.RegNum = RegNum;
2289 Op->PostIdxReg.isAdd = isAdd;
2290 Op->PostIdxReg.ShiftTy = ShiftTy;
2291 Op->PostIdxReg.ShiftImm = ShiftImm;
2297 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2298 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2299 Op->MBOpt.Val = Opt;
2305 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2306 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2307 Op->IFlags.Val = IFlags;
2313 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2314 ARMOperand *Op = new ARMOperand(k_MSRMask);
2315 Op->MMask.Val = MMask;
2322 } // end anonymous namespace.
2324 void ARMOperand::print(raw_ostream &OS) const {
2327 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2330 OS << "<ccout " << getReg() << ">";
2332 case k_ITCondMask: {
2333 static const char *const MaskStr[] = {
2334 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2335 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2337 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2338 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2342 OS << "<coprocessor number: " << getCoproc() << ">";
2345 OS << "<coprocessor register: " << getCoproc() << ">";
2347 case k_CoprocOption:
2348 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2351 OS << "<mask: " << getMSRMask() << ">";
2354 getImm()->print(OS);
2356 case k_MemBarrierOpt:
2357 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2361 << " base:" << Memory.BaseRegNum;
2364 case k_PostIndexRegister:
2365 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2366 << PostIdxReg.RegNum;
2367 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2368 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2369 << PostIdxReg.ShiftImm;
2372 case k_ProcIFlags: {
2373 OS << "<ARM_PROC::";
2374 unsigned IFlags = getProcIFlags();
2375 for (int i=2; i >= 0; --i)
2376 if (IFlags & (1 << i))
2377 OS << ARM_PROC::IFlagsToString(1 << i);
2382 OS << "<register " << getReg() << ">";
2384 case k_ShifterImmediate:
2385 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2386 << " #" << ShifterImm.Imm << ">";
2388 case k_ShiftedRegister:
2389 OS << "<so_reg_reg "
2390 << RegShiftedReg.SrcReg << " "
2391 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2392 << " " << RegShiftedReg.ShiftReg << ">";
2394 case k_ShiftedImmediate:
2395 OS << "<so_reg_imm "
2396 << RegShiftedImm.SrcReg << " "
2397 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2398 << " #" << RegShiftedImm.ShiftImm << ">";
2400 case k_RotateImmediate:
2401 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2403 case k_BitfieldDescriptor:
2404 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2405 << ", width: " << Bitfield.Width << ">";
2407 case k_RegisterList:
2408 case k_DPRRegisterList:
2409 case k_SPRRegisterList: {
2410 OS << "<register_list ";
2412 const SmallVectorImpl<unsigned> &RegList = getRegList();
2413 for (SmallVectorImpl<unsigned>::const_iterator
2414 I = RegList.begin(), E = RegList.end(); I != E; ) {
2416 if (++I < E) OS << ", ";
2423 OS << "<vector_list " << VectorList.Count << " * "
2424 << VectorList.RegNum << ">";
2426 case k_VectorListAllLanes:
2427 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2428 << VectorList.RegNum << ">";
2430 case k_VectorListIndexed:
2431 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2432 << VectorList.Count << " * " << VectorList.RegNum << ">";
2435 OS << "'" << getToken() << "'";
2438 OS << "<vectorindex " << getVectorIndex() << ">";
2443 /// @name Auto-generated Match Functions
2446 static unsigned MatchRegisterName(StringRef Name);
2450 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2451 SMLoc &StartLoc, SMLoc &EndLoc) {
2452 StartLoc = Parser.getTok().getLoc();
2453 RegNo = tryParseRegister();
2454 EndLoc = Parser.getTok().getLoc();
2456 return (RegNo == (unsigned)-1);
2459 /// Try to parse a register name. The token must be an Identifier when called,
2460 /// and if it is a register name the token is eaten and the register number is
2461 /// returned. Otherwise return -1.
2463 int ARMAsmParser::tryParseRegister() {
2464 const AsmToken &Tok = Parser.getTok();
2465 if (Tok.isNot(AsmToken::Identifier)) return -1;
2467 std::string lowerCase = Tok.getString().lower();
2468 unsigned RegNum = MatchRegisterName(lowerCase);
2470 RegNum = StringSwitch<unsigned>(lowerCase)
2471 .Case("r13", ARM::SP)
2472 .Case("r14", ARM::LR)
2473 .Case("r15", ARM::PC)
2474 .Case("ip", ARM::R12)
2475 // Additional register name aliases for 'gas' compatibility.
2476 .Case("a1", ARM::R0)
2477 .Case("a2", ARM::R1)
2478 .Case("a3", ARM::R2)
2479 .Case("a4", ARM::R3)
2480 .Case("v1", ARM::R4)
2481 .Case("v2", ARM::R5)
2482 .Case("v3", ARM::R6)
2483 .Case("v4", ARM::R7)
2484 .Case("v5", ARM::R8)
2485 .Case("v6", ARM::R9)
2486 .Case("v7", ARM::R10)
2487 .Case("v8", ARM::R11)
2488 .Case("sb", ARM::R9)
2489 .Case("sl", ARM::R10)
2490 .Case("fp", ARM::R11)
2494 // Check for aliases registered via .req. Canonicalize to lower case.
2495 // That's more consistent since register names are case insensitive, and
2496 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2497 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2498 // If no match, return failure.
2499 if (Entry == RegisterReqs.end())
2501 Parser.Lex(); // Eat identifier token.
2502 return Entry->getValue();
2505 Parser.Lex(); // Eat identifier token.
2510 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2511 // If a recoverable error occurs, return 1. If an irrecoverable error
2512 // occurs, return -1. An irrecoverable error is one where tokens have been
2513 // consumed in the process of trying to parse the shifter (i.e., when it is
2514 // indeed a shifter operand, but malformed).
2515 int ARMAsmParser::tryParseShiftRegister(
2516 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2517 SMLoc S = Parser.getTok().getLoc();
2518 const AsmToken &Tok = Parser.getTok();
2519 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2521 std::string lowerCase = Tok.getString().lower();
2522 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2523 .Case("asl", ARM_AM::lsl)
2524 .Case("lsl", ARM_AM::lsl)
2525 .Case("lsr", ARM_AM::lsr)
2526 .Case("asr", ARM_AM::asr)
2527 .Case("ror", ARM_AM::ror)
2528 .Case("rrx", ARM_AM::rrx)
2529 .Default(ARM_AM::no_shift);
2531 if (ShiftTy == ARM_AM::no_shift)
2534 Parser.Lex(); // Eat the operator.
2536 // The source register for the shift has already been added to the
2537 // operand list, so we need to pop it off and combine it into the shifted
2538 // register operand instead.
2539 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2540 if (!PrevOp->isReg())
2541 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2542 int SrcReg = PrevOp->getReg();
2545 if (ShiftTy == ARM_AM::rrx) {
2546 // RRX Doesn't have an explicit shift amount. The encoder expects
2547 // the shift register to be the same as the source register. Seems odd,
2551 // Figure out if this is shifted by a constant or a register (for non-RRX).
2552 if (Parser.getTok().is(AsmToken::Hash) ||
2553 Parser.getTok().is(AsmToken::Dollar)) {
2554 Parser.Lex(); // Eat hash.
2555 SMLoc ImmLoc = Parser.getTok().getLoc();
2556 const MCExpr *ShiftExpr = 0;
2557 if (getParser().ParseExpression(ShiftExpr)) {
2558 Error(ImmLoc, "invalid immediate shift value");
2561 // The expression must be evaluatable as an immediate.
2562 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2564 Error(ImmLoc, "invalid immediate shift value");
2567 // Range check the immediate.
2568 // lsl, ror: 0 <= imm <= 31
2569 // lsr, asr: 0 <= imm <= 32
2570 Imm = CE->getValue();
2572 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2573 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2574 Error(ImmLoc, "immediate shift value out of range");
2577 // shift by zero is a nop. Always send it through as lsl.
2578 // ('as' compatibility)
2580 ShiftTy = ARM_AM::lsl;
2581 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2582 ShiftReg = tryParseRegister();
2583 SMLoc L = Parser.getTok().getLoc();
2584 if (ShiftReg == -1) {
2585 Error (L, "expected immediate or register in shift operand");
2589 Error (Parser.getTok().getLoc(),
2590 "expected immediate or register in shift operand");
2595 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2596 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2598 S, Parser.getTok().getLoc()));
2600 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2601 S, Parser.getTok().getLoc()));
2607 /// Try to parse a register name. The token must be an Identifier when called.
2608 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2609 /// if there is a "writeback". 'true' if it's not a register.
2611 /// TODO this is likely to change to allow different register types and or to
2612 /// parse for a specific register type.
2614 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2615 SMLoc S = Parser.getTok().getLoc();
2616 int RegNo = tryParseRegister();
2620 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2622 const AsmToken &ExclaimTok = Parser.getTok();
2623 if (ExclaimTok.is(AsmToken::Exclaim)) {
2624 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2625 ExclaimTok.getLoc()));
2626 Parser.Lex(); // Eat exclaim token
2630 // Also check for an index operand. This is only legal for vector registers,
2631 // but that'll get caught OK in operand matching, so we don't need to
2632 // explicitly filter everything else out here.
2633 if (Parser.getTok().is(AsmToken::LBrac)) {
2634 SMLoc SIdx = Parser.getTok().getLoc();
2635 Parser.Lex(); // Eat left bracket token.
2637 const MCExpr *ImmVal;
2638 if (getParser().ParseExpression(ImmVal))
2640 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2642 return TokError("immediate value expected for vector index");
2644 SMLoc E = Parser.getTok().getLoc();
2645 if (Parser.getTok().isNot(AsmToken::RBrac))
2646 return Error(E, "']' expected");
2648 Parser.Lex(); // Eat right bracket token.
2650 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2658 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2659 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2661 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2662 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2664 switch (Name.size()) {
2667 if (Name[0] != CoprocOp)
2683 if (Name[0] != CoprocOp || Name[1] != '1')
2687 case '0': return 10;
2688 case '1': return 11;
2689 case '2': return 12;
2690 case '3': return 13;
2691 case '4': return 14;
2692 case '5': return 15;
2697 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2698 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2699 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2700 SMLoc S = Parser.getTok().getLoc();
2701 const AsmToken &Tok = Parser.getTok();
2702 if (!Tok.is(AsmToken::Identifier))
2703 return MatchOperand_NoMatch;
2704 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2705 .Case("eq", ARMCC::EQ)
2706 .Case("ne", ARMCC::NE)
2707 .Case("hs", ARMCC::HS)
2708 .Case("cs", ARMCC::HS)
2709 .Case("lo", ARMCC::LO)
2710 .Case("cc", ARMCC::LO)
2711 .Case("mi", ARMCC::MI)
2712 .Case("pl", ARMCC::PL)
2713 .Case("vs", ARMCC::VS)
2714 .Case("vc", ARMCC::VC)
2715 .Case("hi", ARMCC::HI)
2716 .Case("ls", ARMCC::LS)
2717 .Case("ge", ARMCC::GE)
2718 .Case("lt", ARMCC::LT)
2719 .Case("gt", ARMCC::GT)
2720 .Case("le", ARMCC::LE)
2721 .Case("al", ARMCC::AL)
2724 return MatchOperand_NoMatch;
2725 Parser.Lex(); // Eat the token.
2727 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2729 return MatchOperand_Success;
2732 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2733 /// token must be an Identifier when called, and if it is a coprocessor
2734 /// number, the token is eaten and the operand is added to the operand list.
2735 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2736 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2737 SMLoc S = Parser.getTok().getLoc();
2738 const AsmToken &Tok = Parser.getTok();
2739 if (Tok.isNot(AsmToken::Identifier))
2740 return MatchOperand_NoMatch;
2742 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2744 return MatchOperand_NoMatch;
2746 Parser.Lex(); // Eat identifier token.
2747 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2748 return MatchOperand_Success;
2751 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2752 /// token must be an Identifier when called, and if it is a coprocessor
2753 /// number, the token is eaten and the operand is added to the operand list.
2754 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2755 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2756 SMLoc S = Parser.getTok().getLoc();
2757 const AsmToken &Tok = Parser.getTok();
2758 if (Tok.isNot(AsmToken::Identifier))
2759 return MatchOperand_NoMatch;
2761 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2763 return MatchOperand_NoMatch;
2765 Parser.Lex(); // Eat identifier token.
2766 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2767 return MatchOperand_Success;
2770 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2771 /// coproc_option : '{' imm0_255 '}'
2772 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2773 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2774 SMLoc S = Parser.getTok().getLoc();
2776 // If this isn't a '{', this isn't a coprocessor immediate operand.
2777 if (Parser.getTok().isNot(AsmToken::LCurly))
2778 return MatchOperand_NoMatch;
2779 Parser.Lex(); // Eat the '{'
2782 SMLoc Loc = Parser.getTok().getLoc();
2783 if (getParser().ParseExpression(Expr)) {
2784 Error(Loc, "illegal expression");
2785 return MatchOperand_ParseFail;
2787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2788 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2789 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2790 return MatchOperand_ParseFail;
2792 int Val = CE->getValue();
2794 // Check for and consume the closing '}'
2795 if (Parser.getTok().isNot(AsmToken::RCurly))
2796 return MatchOperand_ParseFail;
2797 SMLoc E = Parser.getTok().getLoc();
2798 Parser.Lex(); // Eat the '}'
2800 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2801 return MatchOperand_Success;
2804 // For register list parsing, we need to map from raw GPR register numbering
2805 // to the enumeration values. The enumeration values aren't sorted by
2806 // register number due to our using "sp", "lr" and "pc" as canonical names.
2807 static unsigned getNextRegister(unsigned Reg) {
2808 // If this is a GPR, we need to do it manually, otherwise we can rely
2809 // on the sort ordering of the enumeration since the other reg-classes
2811 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2814 default: llvm_unreachable("Invalid GPR number!");
2815 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2816 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2817 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2818 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2819 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2820 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2821 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2822 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2826 // Return the low-subreg of a given Q register.
2827 static unsigned getDRegFromQReg(unsigned QReg) {
2829 default: llvm_unreachable("expected a Q register!");
2830 case ARM::Q0: return ARM::D0;
2831 case ARM::Q1: return ARM::D2;
2832 case ARM::Q2: return ARM::D4;
2833 case ARM::Q3: return ARM::D6;
2834 case ARM::Q4: return ARM::D8;
2835 case ARM::Q5: return ARM::D10;
2836 case ARM::Q6: return ARM::D12;
2837 case ARM::Q7: return ARM::D14;
2838 case ARM::Q8: return ARM::D16;
2839 case ARM::Q9: return ARM::D18;
2840 case ARM::Q10: return ARM::D20;
2841 case ARM::Q11: return ARM::D22;
2842 case ARM::Q12: return ARM::D24;
2843 case ARM::Q13: return ARM::D26;
2844 case ARM::Q14: return ARM::D28;
2845 case ARM::Q15: return ARM::D30;
2849 /// Parse a register list.
2851 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2852 assert(Parser.getTok().is(AsmToken::LCurly) &&
2853 "Token is not a Left Curly Brace");
2854 SMLoc S = Parser.getTok().getLoc();
2855 Parser.Lex(); // Eat '{' token.
2856 SMLoc RegLoc = Parser.getTok().getLoc();
2858 // Check the first register in the list to see what register class
2859 // this is a list of.
2860 int Reg = tryParseRegister();
2862 return Error(RegLoc, "register expected");
2864 // The reglist instructions have at most 16 registers, so reserve
2865 // space for that many.
2866 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2868 // Allow Q regs and just interpret them as the two D sub-registers.
2869 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2870 Reg = getDRegFromQReg(Reg);
2871 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2874 const MCRegisterClass *RC;
2875 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2876 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2877 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2878 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2879 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2880 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2882 return Error(RegLoc, "invalid register in register list");
2884 // Store the register.
2885 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2887 // This starts immediately after the first register token in the list,
2888 // so we can see either a comma or a minus (range separator) as a legal
2890 while (Parser.getTok().is(AsmToken::Comma) ||
2891 Parser.getTok().is(AsmToken::Minus)) {
2892 if (Parser.getTok().is(AsmToken::Minus)) {
2893 Parser.Lex(); // Eat the minus.
2894 SMLoc EndLoc = Parser.getTok().getLoc();
2895 int EndReg = tryParseRegister();
2897 return Error(EndLoc, "register expected");
2898 // Allow Q regs and just interpret them as the two D sub-registers.
2899 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2900 EndReg = getDRegFromQReg(EndReg) + 1;
2901 // If the register is the same as the start reg, there's nothing
2905 // The register must be in the same register class as the first.
2906 if (!RC->contains(EndReg))
2907 return Error(EndLoc, "invalid register in register list");
2908 // Ranges must go from low to high.
2909 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2910 return Error(EndLoc, "bad range in register list");
2912 // Add all the registers in the range to the register list.
2913 while (Reg != EndReg) {
2914 Reg = getNextRegister(Reg);
2915 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2919 Parser.Lex(); // Eat the comma.
2920 RegLoc = Parser.getTok().getLoc();
2922 const AsmToken RegTok = Parser.getTok();
2923 Reg = tryParseRegister();
2925 return Error(RegLoc, "register expected");
2926 // Allow Q regs and just interpret them as the two D sub-registers.
2927 bool isQReg = false;
2928 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2929 Reg = getDRegFromQReg(Reg);
2932 // The register must be in the same register class as the first.
2933 if (!RC->contains(Reg))
2934 return Error(RegLoc, "invalid register in register list");
2935 // List must be monotonically increasing.
2936 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2937 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2938 Warning(RegLoc, "register list not in ascending order");
2940 return Error(RegLoc, "register list not in ascending order");
2942 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2943 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2944 ") in register list");
2947 // VFP register lists must also be contiguous.
2948 // It's OK to use the enumeration values directly here rather, as the
2949 // VFP register classes have the enum sorted properly.
2950 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2952 return Error(RegLoc, "non-contiguous register range");
2953 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2955 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2958 SMLoc E = Parser.getTok().getLoc();
2959 if (Parser.getTok().isNot(AsmToken::RCurly))
2960 return Error(E, "'}' expected");
2961 Parser.Lex(); // Eat '}' token.
2963 // Push the register list operand.
2964 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2966 // The ARM system instruction variants for LDM/STM have a '^' token here.
2967 if (Parser.getTok().is(AsmToken::Caret)) {
2968 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2969 Parser.Lex(); // Eat '^' token.
2975 // Helper function to parse the lane index for vector lists.
2976 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2977 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2978 Index = 0; // Always return a defined index value.
2979 if (Parser.getTok().is(AsmToken::LBrac)) {
2980 Parser.Lex(); // Eat the '['.
2981 if (Parser.getTok().is(AsmToken::RBrac)) {
2982 // "Dn[]" is the 'all lanes' syntax.
2983 LaneKind = AllLanes;
2984 Parser.Lex(); // Eat the ']'.
2985 return MatchOperand_Success;
2988 // There's an optional '#' token here. Normally there wouldn't be, but
2989 // inline assemble puts one in, and it's friendly to accept that.
2990 if (Parser.getTok().is(AsmToken::Hash))
2991 Parser.Lex(); // Eat the '#'
2993 const MCExpr *LaneIndex;
2994 SMLoc Loc = Parser.getTok().getLoc();
2995 if (getParser().ParseExpression(LaneIndex)) {
2996 Error(Loc, "illegal expression");
2997 return MatchOperand_ParseFail;
2999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3001 Error(Loc, "lane index must be empty or an integer");
3002 return MatchOperand_ParseFail;
3004 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3005 Error(Parser.getTok().getLoc(), "']' expected");
3006 return MatchOperand_ParseFail;
3008 Parser.Lex(); // Eat the ']'.
3009 int64_t Val = CE->getValue();
3011 // FIXME: Make this range check context sensitive for .8, .16, .32.
3012 if (Val < 0 || Val > 7) {
3013 Error(Parser.getTok().getLoc(), "lane index out of range");
3014 return MatchOperand_ParseFail;
3017 LaneKind = IndexedLane;
3018 return MatchOperand_Success;
3021 return MatchOperand_Success;
3024 // parse a vector register list
3025 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3026 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3027 VectorLaneTy LaneKind;
3029 SMLoc S = Parser.getTok().getLoc();
3030 // As an extension (to match gas), support a plain D register or Q register
3031 // (without encosing curly braces) as a single or double entry list,
3033 if (Parser.getTok().is(AsmToken::Identifier)) {
3034 int Reg = tryParseRegister();
3036 return MatchOperand_NoMatch;
3037 SMLoc E = Parser.getTok().getLoc();
3038 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3039 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3040 if (Res != MatchOperand_Success)
3044 E = Parser.getTok().getLoc();
3045 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3048 E = Parser.getTok().getLoc();
3049 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3053 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3058 return MatchOperand_Success;
3060 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3061 Reg = getDRegFromQReg(Reg);
3062 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3063 if (Res != MatchOperand_Success)
3067 E = Parser.getTok().getLoc();
3068 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3069 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3070 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3073 E = Parser.getTok().getLoc();
3074 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3075 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3076 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3080 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3085 return MatchOperand_Success;
3087 Error(S, "vector register expected");
3088 return MatchOperand_ParseFail;
3091 if (Parser.getTok().isNot(AsmToken::LCurly))
3092 return MatchOperand_NoMatch;
3094 Parser.Lex(); // Eat '{' token.
3095 SMLoc RegLoc = Parser.getTok().getLoc();
3097 int Reg = tryParseRegister();
3099 Error(RegLoc, "register expected");
3100 return MatchOperand_ParseFail;
3104 unsigned FirstReg = Reg;
3105 // The list is of D registers, but we also allow Q regs and just interpret
3106 // them as the two D sub-registers.
3107 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3108 FirstReg = Reg = getDRegFromQReg(Reg);
3109 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3110 // it's ambiguous with four-register single spaced.
3114 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3115 return MatchOperand_ParseFail;
3117 while (Parser.getTok().is(AsmToken::Comma) ||
3118 Parser.getTok().is(AsmToken::Minus)) {
3119 if (Parser.getTok().is(AsmToken::Minus)) {
3121 Spacing = 1; // Register range implies a single spaced list.
3122 else if (Spacing == 2) {
3123 Error(Parser.getTok().getLoc(),
3124 "sequential registers in double spaced list");
3125 return MatchOperand_ParseFail;
3127 Parser.Lex(); // Eat the minus.
3128 SMLoc EndLoc = Parser.getTok().getLoc();
3129 int EndReg = tryParseRegister();
3131 Error(EndLoc, "register expected");
3132 return MatchOperand_ParseFail;
3134 // Allow Q regs and just interpret them as the two D sub-registers.
3135 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3136 EndReg = getDRegFromQReg(EndReg) + 1;
3137 // If the register is the same as the start reg, there's nothing
3141 // The register must be in the same register class as the first.
3142 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3143 Error(EndLoc, "invalid register in register list");
3144 return MatchOperand_ParseFail;
3146 // Ranges must go from low to high.
3148 Error(EndLoc, "bad range in register list");
3149 return MatchOperand_ParseFail;
3151 // Parse the lane specifier if present.
3152 VectorLaneTy NextLaneKind;
3153 unsigned NextLaneIndex;
3154 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3155 return MatchOperand_ParseFail;
3156 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3157 Error(EndLoc, "mismatched lane index in register list");
3158 return MatchOperand_ParseFail;
3160 EndLoc = Parser.getTok().getLoc();
3162 // Add all the registers in the range to the register list.
3163 Count += EndReg - Reg;
3167 Parser.Lex(); // Eat the comma.
3168 RegLoc = Parser.getTok().getLoc();
3170 Reg = tryParseRegister();
3172 Error(RegLoc, "register expected");
3173 return MatchOperand_ParseFail;
3175 // vector register lists must be contiguous.
3176 // It's OK to use the enumeration values directly here rather, as the
3177 // VFP register classes have the enum sorted properly.
3179 // The list is of D registers, but we also allow Q regs and just interpret
3180 // them as the two D sub-registers.
3181 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3183 Spacing = 1; // Register range implies a single spaced list.
3184 else if (Spacing == 2) {
3186 "invalid register in double-spaced list (must be 'D' register')");
3187 return MatchOperand_ParseFail;
3189 Reg = getDRegFromQReg(Reg);
3190 if (Reg != OldReg + 1) {
3191 Error(RegLoc, "non-contiguous register range");
3192 return MatchOperand_ParseFail;
3196 // Parse the lane specifier if present.
3197 VectorLaneTy NextLaneKind;
3198 unsigned NextLaneIndex;
3199 SMLoc EndLoc = Parser.getTok().getLoc();
3200 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3201 return MatchOperand_ParseFail;
3202 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3203 Error(EndLoc, "mismatched lane index in register list");
3204 return MatchOperand_ParseFail;
3208 // Normal D register.
3209 // Figure out the register spacing (single or double) of the list if
3210 // we don't know it already.
3212 Spacing = 1 + (Reg == OldReg + 2);
3214 // Just check that it's contiguous and keep going.
3215 if (Reg != OldReg + Spacing) {
3216 Error(RegLoc, "non-contiguous register range");
3217 return MatchOperand_ParseFail;
3220 // Parse the lane specifier if present.
3221 VectorLaneTy NextLaneKind;
3222 unsigned NextLaneIndex;
3223 SMLoc EndLoc = Parser.getTok().getLoc();
3224 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3225 return MatchOperand_ParseFail;
3226 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3227 Error(EndLoc, "mismatched lane index in register list");
3228 return MatchOperand_ParseFail;
3232 SMLoc E = Parser.getTok().getLoc();
3233 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3234 Error(E, "'}' expected");
3235 return MatchOperand_ParseFail;
3237 Parser.Lex(); // Eat '}' token.
3241 // Two-register operands have been converted to the
3242 // composite register classes.
3244 const MCRegisterClass *RC = (Spacing == 1) ?
3245 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3246 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3247 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3250 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3251 (Spacing == 2), S, E));
3254 // Two-register operands have been converted to the
3255 // composite register classes.
3257 const MCRegisterClass *RC = (Spacing == 1) ?
3258 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3259 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3260 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3262 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3267 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3273 return MatchOperand_Success;
3276 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3277 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3278 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3279 SMLoc S = Parser.getTok().getLoc();
3280 const AsmToken &Tok = Parser.getTok();
3283 if (Tok.is(AsmToken::Identifier)) {
3284 StringRef OptStr = Tok.getString();
3286 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3287 .Case("sy", ARM_MB::SY)
3288 .Case("st", ARM_MB::ST)
3289 .Case("sh", ARM_MB::ISH)
3290 .Case("ish", ARM_MB::ISH)
3291 .Case("shst", ARM_MB::ISHST)
3292 .Case("ishst", ARM_MB::ISHST)
3293 .Case("nsh", ARM_MB::NSH)
3294 .Case("un", ARM_MB::NSH)
3295 .Case("nshst", ARM_MB::NSHST)
3296 .Case("unst", ARM_MB::NSHST)
3297 .Case("osh", ARM_MB::OSH)
3298 .Case("oshst", ARM_MB::OSHST)
3302 return MatchOperand_NoMatch;
3304 Parser.Lex(); // Eat identifier token.
3305 } else if (Tok.is(AsmToken::Hash) ||
3306 Tok.is(AsmToken::Dollar) ||
3307 Tok.is(AsmToken::Integer)) {
3308 if (Parser.getTok().isNot(AsmToken::Integer))
3309 Parser.Lex(); // Eat the '#'.
3310 SMLoc Loc = Parser.getTok().getLoc();
3312 const MCExpr *MemBarrierID;
3313 if (getParser().ParseExpression(MemBarrierID)) {
3314 Error(Loc, "illegal expression");
3315 return MatchOperand_ParseFail;
3318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3320 Error(Loc, "constant expression expected");
3321 return MatchOperand_ParseFail;
3324 int Val = CE->getValue();
3326 Error(Loc, "immediate value out of range");
3327 return MatchOperand_ParseFail;
3330 Opt = ARM_MB::RESERVED_0 + Val;
3332 return MatchOperand_ParseFail;
3334 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3335 return MatchOperand_Success;
3338 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3339 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3340 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3341 SMLoc S = Parser.getTok().getLoc();
3342 const AsmToken &Tok = Parser.getTok();
3343 if (!Tok.is(AsmToken::Identifier))
3344 return MatchOperand_NoMatch;
3345 StringRef IFlagsStr = Tok.getString();
3347 // An iflags string of "none" is interpreted to mean that none of the AIF
3348 // bits are set. Not a terribly useful instruction, but a valid encoding.
3349 unsigned IFlags = 0;
3350 if (IFlagsStr != "none") {
3351 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3352 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3353 .Case("a", ARM_PROC::A)
3354 .Case("i", ARM_PROC::I)
3355 .Case("f", ARM_PROC::F)
3358 // If some specific iflag is already set, it means that some letter is
3359 // present more than once, this is not acceptable.
3360 if (Flag == ~0U || (IFlags & Flag))
3361 return MatchOperand_NoMatch;
3367 Parser.Lex(); // Eat identifier token.
3368 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3369 return MatchOperand_Success;
3372 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3373 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3374 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3375 SMLoc S = Parser.getTok().getLoc();
3376 const AsmToken &Tok = Parser.getTok();
3377 if (!Tok.is(AsmToken::Identifier))
3378 return MatchOperand_NoMatch;
3379 StringRef Mask = Tok.getString();
3382 // See ARMv6-M 10.1.1
3383 std::string Name = Mask.lower();
3384 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3385 // Note: in the documentation:
3386 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3387 // for MSR APSR_nzcvq.
3388 // but we do make it an alias here. This is so to get the "mask encoding"
3389 // bits correct on MSR APSR writes.
3391 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3392 // should really only be allowed when writing a special register. Note
3393 // they get dropped in the MRS instruction reading a special register as
3394 // the SYSm field is only 8 bits.
3396 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3397 // includes the DSP extension but that is not checked.
3398 .Case("apsr", 0x800)
3399 .Case("apsr_nzcvq", 0x800)
3400 .Case("apsr_g", 0x400)
3401 .Case("apsr_nzcvqg", 0xc00)
3402 .Case("iapsr", 0x801)
3403 .Case("iapsr_nzcvq", 0x801)
3404 .Case("iapsr_g", 0x401)
3405 .Case("iapsr_nzcvqg", 0xc01)
3406 .Case("eapsr", 0x802)
3407 .Case("eapsr_nzcvq", 0x802)
3408 .Case("eapsr_g", 0x402)
3409 .Case("eapsr_nzcvqg", 0xc02)
3410 .Case("xpsr", 0x803)
3411 .Case("xpsr_nzcvq", 0x803)
3412 .Case("xpsr_g", 0x403)
3413 .Case("xpsr_nzcvqg", 0xc03)
3414 .Case("ipsr", 0x805)
3415 .Case("epsr", 0x806)
3416 .Case("iepsr", 0x807)
3419 .Case("primask", 0x810)
3420 .Case("basepri", 0x811)
3421 .Case("basepri_max", 0x812)
3422 .Case("faultmask", 0x813)
3423 .Case("control", 0x814)
3426 if (FlagsVal == ~0U)
3427 return MatchOperand_NoMatch;
3429 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3430 // basepri, basepri_max and faultmask only valid for V7m.
3431 return MatchOperand_NoMatch;
3433 Parser.Lex(); // Eat identifier token.
3434 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3435 return MatchOperand_Success;
3438 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3439 size_t Start = 0, Next = Mask.find('_');
3440 StringRef Flags = "";
3441 std::string SpecReg = Mask.slice(Start, Next).lower();
3442 if (Next != StringRef::npos)
3443 Flags = Mask.slice(Next+1, Mask.size());
3445 // FlagsVal contains the complete mask:
3447 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3448 unsigned FlagsVal = 0;
3450 if (SpecReg == "apsr") {
3451 FlagsVal = StringSwitch<unsigned>(Flags)
3452 .Case("nzcvq", 0x8) // same as CPSR_f
3453 .Case("g", 0x4) // same as CPSR_s
3454 .Case("nzcvqg", 0xc) // same as CPSR_fs
3457 if (FlagsVal == ~0U) {
3459 return MatchOperand_NoMatch;
3461 FlagsVal = 8; // No flag
3463 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3464 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3465 if (Flags == "all" || Flags == "")
3467 for (int i = 0, e = Flags.size(); i != e; ++i) {
3468 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3475 // If some specific flag is already set, it means that some letter is
3476 // present more than once, this is not acceptable.
3477 if (FlagsVal == ~0U || (FlagsVal & Flag))
3478 return MatchOperand_NoMatch;
3481 } else // No match for special register.
3482 return MatchOperand_NoMatch;
3484 // Special register without flags is NOT equivalent to "fc" flags.
3485 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3486 // two lines would enable gas compatibility at the expense of breaking
3492 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3493 if (SpecReg == "spsr")
3496 Parser.Lex(); // Eat identifier token.
3497 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3498 return MatchOperand_Success;
3501 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3502 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3503 int Low, int High) {
3504 const AsmToken &Tok = Parser.getTok();
3505 if (Tok.isNot(AsmToken::Identifier)) {
3506 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3507 return MatchOperand_ParseFail;
3509 StringRef ShiftName = Tok.getString();
3510 std::string LowerOp = Op.lower();
3511 std::string UpperOp = Op.upper();
3512 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3513 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3514 return MatchOperand_ParseFail;
3516 Parser.Lex(); // Eat shift type token.
3518 // There must be a '#' and a shift amount.
3519 if (Parser.getTok().isNot(AsmToken::Hash) &&
3520 Parser.getTok().isNot(AsmToken::Dollar)) {
3521 Error(Parser.getTok().getLoc(), "'#' expected");
3522 return MatchOperand_ParseFail;
3524 Parser.Lex(); // Eat hash token.
3526 const MCExpr *ShiftAmount;
3527 SMLoc Loc = Parser.getTok().getLoc();
3528 if (getParser().ParseExpression(ShiftAmount)) {
3529 Error(Loc, "illegal expression");
3530 return MatchOperand_ParseFail;
3532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3534 Error(Loc, "constant expression expected");
3535 return MatchOperand_ParseFail;
3537 int Val = CE->getValue();
3538 if (Val < Low || Val > High) {
3539 Error(Loc, "immediate value out of range");
3540 return MatchOperand_ParseFail;
3543 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3545 return MatchOperand_Success;
3548 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3549 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3550 const AsmToken &Tok = Parser.getTok();
3551 SMLoc S = Tok.getLoc();
3552 if (Tok.isNot(AsmToken::Identifier)) {
3553 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3554 return MatchOperand_ParseFail;
3556 int Val = StringSwitch<int>(Tok.getString())
3560 Parser.Lex(); // Eat the token.
3563 Error(Tok.getLoc(), "'be' or 'le' operand expected");
3564 return MatchOperand_ParseFail;
3566 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3568 S, Parser.getTok().getLoc()));
3569 return MatchOperand_Success;
3572 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3573 /// instructions. Legal values are:
3574 /// lsl #n 'n' in [0,31]
3575 /// asr #n 'n' in [1,32]
3576 /// n == 32 encoded as n == 0.
3577 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3578 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3579 const AsmToken &Tok = Parser.getTok();
3580 SMLoc S = Tok.getLoc();
3581 if (Tok.isNot(AsmToken::Identifier)) {
3582 Error(S, "shift operator 'asr' or 'lsl' expected");
3583 return MatchOperand_ParseFail;
3585 StringRef ShiftName = Tok.getString();
3587 if (ShiftName == "lsl" || ShiftName == "LSL")
3589 else if (ShiftName == "asr" || ShiftName == "ASR")
3592 Error(S, "shift operator 'asr' or 'lsl' expected");
3593 return MatchOperand_ParseFail;
3595 Parser.Lex(); // Eat the operator.
3597 // A '#' and a shift amount.
3598 if (Parser.getTok().isNot(AsmToken::Hash) &&
3599 Parser.getTok().isNot(AsmToken::Dollar)) {
3600 Error(Parser.getTok().getLoc(), "'#' expected");
3601 return MatchOperand_ParseFail;
3603 Parser.Lex(); // Eat hash token.
3605 const MCExpr *ShiftAmount;
3606 SMLoc E = Parser.getTok().getLoc();
3607 if (getParser().ParseExpression(ShiftAmount)) {
3608 Error(E, "malformed shift expression");
3609 return MatchOperand_ParseFail;
3611 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3613 Error(E, "shift amount must be an immediate");
3614 return MatchOperand_ParseFail;
3617 int64_t Val = CE->getValue();
3619 // Shift amount must be in [1,32]
3620 if (Val < 1 || Val > 32) {
3621 Error(E, "'asr' shift amount must be in range [1,32]");
3622 return MatchOperand_ParseFail;
3624 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3625 if (isThumb() && Val == 32) {
3626 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3627 return MatchOperand_ParseFail;
3629 if (Val == 32) Val = 0;
3631 // Shift amount must be in [1,32]
3632 if (Val < 0 || Val > 31) {
3633 Error(E, "'lsr' shift amount must be in range [0,31]");
3634 return MatchOperand_ParseFail;
3638 E = Parser.getTok().getLoc();
3639 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3641 return MatchOperand_Success;
3644 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3645 /// of instructions. Legal values are:
3646 /// ror #n 'n' in {0, 8, 16, 24}
3647 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3648 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3649 const AsmToken &Tok = Parser.getTok();
3650 SMLoc S = Tok.getLoc();
3651 if (Tok.isNot(AsmToken::Identifier))
3652 return MatchOperand_NoMatch;
3653 StringRef ShiftName = Tok.getString();
3654 if (ShiftName != "ror" && ShiftName != "ROR")
3655 return MatchOperand_NoMatch;
3656 Parser.Lex(); // Eat the operator.
3658 // A '#' and a rotate amount.
3659 if (Parser.getTok().isNot(AsmToken::Hash) &&
3660 Parser.getTok().isNot(AsmToken::Dollar)) {
3661 Error(Parser.getTok().getLoc(), "'#' expected");
3662 return MatchOperand_ParseFail;
3664 Parser.Lex(); // Eat hash token.
3666 const MCExpr *ShiftAmount;
3667 SMLoc E = Parser.getTok().getLoc();
3668 if (getParser().ParseExpression(ShiftAmount)) {
3669 Error(E, "malformed rotate expression");
3670 return MatchOperand_ParseFail;
3672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3674 Error(E, "rotate amount must be an immediate");
3675 return MatchOperand_ParseFail;
3678 int64_t Val = CE->getValue();
3679 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3680 // normally, zero is represented in asm by omitting the rotate operand
3682 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3683 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3684 return MatchOperand_ParseFail;
3687 E = Parser.getTok().getLoc();
3688 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3690 return MatchOperand_Success;
3693 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3694 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3695 SMLoc S = Parser.getTok().getLoc();
3696 // The bitfield descriptor is really two operands, the LSB and the width.
3697 if (Parser.getTok().isNot(AsmToken::Hash) &&
3698 Parser.getTok().isNot(AsmToken::Dollar)) {
3699 Error(Parser.getTok().getLoc(), "'#' expected");
3700 return MatchOperand_ParseFail;
3702 Parser.Lex(); // Eat hash token.
3704 const MCExpr *LSBExpr;
3705 SMLoc E = Parser.getTok().getLoc();
3706 if (getParser().ParseExpression(LSBExpr)) {
3707 Error(E, "malformed immediate expression");
3708 return MatchOperand_ParseFail;
3710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3712 Error(E, "'lsb' operand must be an immediate");
3713 return MatchOperand_ParseFail;
3716 int64_t LSB = CE->getValue();
3717 // The LSB must be in the range [0,31]
3718 if (LSB < 0 || LSB > 31) {
3719 Error(E, "'lsb' operand must be in the range [0,31]");
3720 return MatchOperand_ParseFail;
3722 E = Parser.getTok().getLoc();
3724 // Expect another immediate operand.
3725 if (Parser.getTok().isNot(AsmToken::Comma)) {
3726 Error(Parser.getTok().getLoc(), "too few operands");
3727 return MatchOperand_ParseFail;
3729 Parser.Lex(); // Eat hash token.
3730 if (Parser.getTok().isNot(AsmToken::Hash) &&
3731 Parser.getTok().isNot(AsmToken::Dollar)) {
3732 Error(Parser.getTok().getLoc(), "'#' expected");
3733 return MatchOperand_ParseFail;
3735 Parser.Lex(); // Eat hash token.
3737 const MCExpr *WidthExpr;
3738 if (getParser().ParseExpression(WidthExpr)) {
3739 Error(E, "malformed immediate expression");
3740 return MatchOperand_ParseFail;
3742 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3744 Error(E, "'width' operand must be an immediate");
3745 return MatchOperand_ParseFail;
3748 int64_t Width = CE->getValue();
3749 // The LSB must be in the range [1,32-lsb]
3750 if (Width < 1 || Width > 32 - LSB) {
3751 Error(E, "'width' operand must be in the range [1,32-lsb]");
3752 return MatchOperand_ParseFail;
3754 E = Parser.getTok().getLoc();
3756 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3758 return MatchOperand_Success;
3761 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3762 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3763 // Check for a post-index addressing register operand. Specifically:
3764 // postidx_reg := '+' register {, shift}
3765 // | '-' register {, shift}
3766 // | register {, shift}
3768 // This method must return MatchOperand_NoMatch without consuming any tokens
3769 // in the case where there is no match, as other alternatives take other
3771 AsmToken Tok = Parser.getTok();
3772 SMLoc S = Tok.getLoc();
3773 bool haveEaten = false;
3776 if (Tok.is(AsmToken::Plus)) {
3777 Parser.Lex(); // Eat the '+' token.
3779 } else if (Tok.is(AsmToken::Minus)) {
3780 Parser.Lex(); // Eat the '-' token.
3784 if (Parser.getTok().is(AsmToken::Identifier))
3785 Reg = tryParseRegister();
3788 return MatchOperand_NoMatch;
3789 Error(Parser.getTok().getLoc(), "register expected");
3790 return MatchOperand_ParseFail;
3792 SMLoc E = Parser.getTok().getLoc();
3794 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3795 unsigned ShiftImm = 0;
3796 if (Parser.getTok().is(AsmToken::Comma)) {
3797 Parser.Lex(); // Eat the ','.
3798 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3799 return MatchOperand_ParseFail;
3802 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3805 return MatchOperand_Success;
3808 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3809 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3810 // Check for a post-index addressing register operand. Specifically:
3811 // am3offset := '+' register
3818 // This method must return MatchOperand_NoMatch without consuming any tokens
3819 // in the case where there is no match, as other alternatives take other
3821 AsmToken Tok = Parser.getTok();
3822 SMLoc S = Tok.getLoc();
3824 // Do immediates first, as we always parse those if we have a '#'.
3825 if (Parser.getTok().is(AsmToken::Hash) ||
3826 Parser.getTok().is(AsmToken::Dollar)) {
3827 Parser.Lex(); // Eat the '#'.
3828 // Explicitly look for a '-', as we need to encode negative zero
3830 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3831 const MCExpr *Offset;
3832 if (getParser().ParseExpression(Offset))
3833 return MatchOperand_ParseFail;
3834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3836 Error(S, "constant expression expected");
3837 return MatchOperand_ParseFail;
3839 SMLoc E = Tok.getLoc();
3840 // Negative zero is encoded as the flag value INT32_MIN.
3841 int32_t Val = CE->getValue();
3842 if (isNegative && Val == 0)
3846 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3848 return MatchOperand_Success;
3852 bool haveEaten = false;
3855 if (Tok.is(AsmToken::Plus)) {
3856 Parser.Lex(); // Eat the '+' token.
3858 } else if (Tok.is(AsmToken::Minus)) {
3859 Parser.Lex(); // Eat the '-' token.
3863 if (Parser.getTok().is(AsmToken::Identifier))
3864 Reg = tryParseRegister();
3867 return MatchOperand_NoMatch;
3868 Error(Parser.getTok().getLoc(), "register expected");
3869 return MatchOperand_ParseFail;
3871 SMLoc E = Parser.getTok().getLoc();
3873 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3876 return MatchOperand_Success;
3879 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3880 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3881 /// when they refer multiple MIOperands inside a single one.
3883 cvtT2LdrdPre(MCInst &Inst,
3884 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3887 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3888 // Create a writeback register dummy placeholder.
3889 Inst.addOperand(MCOperand::CreateReg(0));
3891 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3893 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3896 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3897 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3898 /// when they refer multiple MIOperands inside a single one.
3900 cvtT2StrdPre(MCInst &Inst,
3901 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3902 // Create a writeback register dummy placeholder.
3903 Inst.addOperand(MCOperand::CreateReg(0));
3905 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3906 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3908 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3910 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3913 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3914 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3915 /// when they refer multiple MIOperands inside a single one.
3917 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3918 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3919 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3921 // Create a writeback register dummy placeholder.
3922 Inst.addOperand(MCOperand::CreateImm(0));
3924 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3925 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3928 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3929 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3930 /// when they refer multiple MIOperands inside a single one.
3932 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3933 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3934 // Create a writeback register dummy placeholder.
3935 Inst.addOperand(MCOperand::CreateImm(0));
3936 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3937 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3938 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3941 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3942 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3943 /// when they refer multiple MIOperands inside a single one.
3945 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3946 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3947 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3949 // Create a writeback register dummy placeholder.
3950 Inst.addOperand(MCOperand::CreateImm(0));
3952 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3953 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3956 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3957 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3958 /// when they refer multiple MIOperands inside a single one.
3960 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
3961 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3962 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3964 // Create a writeback register dummy placeholder.
3965 Inst.addOperand(MCOperand::CreateImm(0));
3967 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3968 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3972 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3973 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3974 /// when they refer multiple MIOperands inside a single one.
3976 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
3977 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3978 // Create a writeback register dummy placeholder.
3979 Inst.addOperand(MCOperand::CreateImm(0));
3980 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3981 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3982 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3985 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3986 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3987 /// when they refer multiple MIOperands inside a single one.
3989 cvtStWriteBackRegAddrMode2(MCInst &Inst,
3990 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3991 // Create a writeback register dummy placeholder.
3992 Inst.addOperand(MCOperand::CreateImm(0));
3993 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3994 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3995 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3998 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3999 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4000 /// when they refer multiple MIOperands inside a single one.
4002 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4003 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4004 // Create a writeback register dummy placeholder.
4005 Inst.addOperand(MCOperand::CreateImm(0));
4006 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4007 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4008 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4011 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4012 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4013 /// when they refer multiple MIOperands inside a single one.
4015 cvtLdExtTWriteBackImm(MCInst &Inst,
4016 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4018 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4019 // Create a writeback register dummy placeholder.
4020 Inst.addOperand(MCOperand::CreateImm(0));
4022 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4024 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4026 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4029 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4030 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4031 /// when they refer multiple MIOperands inside a single one.
4033 cvtLdExtTWriteBackReg(MCInst &Inst,
4034 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4036 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4037 // Create a writeback register dummy placeholder.
4038 Inst.addOperand(MCOperand::CreateImm(0));
4040 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4042 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4044 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4047 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4048 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4049 /// when they refer multiple MIOperands inside a single one.
4051 cvtStExtTWriteBackImm(MCInst &Inst,
4052 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4053 // Create a writeback register dummy placeholder.
4054 Inst.addOperand(MCOperand::CreateImm(0));
4056 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4058 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4060 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4062 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4065 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4066 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4067 /// when they refer multiple MIOperands inside a single one.
4069 cvtStExtTWriteBackReg(MCInst &Inst,
4070 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4071 // Create a writeback register dummy placeholder.
4072 Inst.addOperand(MCOperand::CreateImm(0));
4074 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4076 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4078 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4080 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4083 /// cvtLdrdPre - Convert parsed operands to MCInst.
4084 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4085 /// when they refer multiple MIOperands inside a single one.
4087 cvtLdrdPre(MCInst &Inst,
4088 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4090 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4091 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4092 // Create a writeback register dummy placeholder.
4093 Inst.addOperand(MCOperand::CreateImm(0));
4095 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4097 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4100 /// cvtStrdPre - Convert parsed operands to MCInst.
4101 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4102 /// when they refer multiple MIOperands inside a single one.
4104 cvtStrdPre(MCInst &Inst,
4105 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4106 // Create a writeback register dummy placeholder.
4107 Inst.addOperand(MCOperand::CreateImm(0));
4109 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4110 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4112 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4114 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4117 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4118 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4119 /// when they refer multiple MIOperands inside a single one.
4121 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4122 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4123 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4124 // Create a writeback register dummy placeholder.
4125 Inst.addOperand(MCOperand::CreateImm(0));
4126 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4127 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4130 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4131 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4132 /// when they refer multiple MIOperands inside a single one.
4134 cvtThumbMultiply(MCInst &Inst,
4135 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4136 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4137 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4138 // If we have a three-operand form, make sure to set Rn to be the operand
4139 // that isn't the same as Rd.
4141 if (Operands.size() == 6 &&
4142 ((ARMOperand*)Operands[4])->getReg() ==
4143 ((ARMOperand*)Operands[3])->getReg())
4145 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4146 Inst.addOperand(Inst.getOperand(0));
4147 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4151 cvtVLDwbFixed(MCInst &Inst,
4152 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4154 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4155 // Create a writeback register dummy placeholder.
4156 Inst.addOperand(MCOperand::CreateImm(0));
4158 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4160 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4164 cvtVLDwbRegister(MCInst &Inst,
4165 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4167 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4168 // Create a writeback register dummy placeholder.
4169 Inst.addOperand(MCOperand::CreateImm(0));
4171 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4173 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4175 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4179 cvtVSTwbFixed(MCInst &Inst,
4180 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4181 // Create a writeback register dummy placeholder.
4182 Inst.addOperand(MCOperand::CreateImm(0));
4184 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4186 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4188 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4192 cvtVSTwbRegister(MCInst &Inst,
4193 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4194 // Create a writeback register dummy placeholder.
4195 Inst.addOperand(MCOperand::CreateImm(0));
4197 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4199 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4201 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4203 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4206 /// Parse an ARM memory expression, return false if successful else return true
4207 /// or an error. The first token must be a '[' when called.
4209 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4211 assert(Parser.getTok().is(AsmToken::LBrac) &&
4212 "Token is not a Left Bracket");
4213 S = Parser.getTok().getLoc();
4214 Parser.Lex(); // Eat left bracket token.
4216 const AsmToken &BaseRegTok = Parser.getTok();
4217 int BaseRegNum = tryParseRegister();
4218 if (BaseRegNum == -1)
4219 return Error(BaseRegTok.getLoc(), "register expected");
4221 // The next token must either be a comma or a closing bracket.
4222 const AsmToken &Tok = Parser.getTok();
4223 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4224 return Error(Tok.getLoc(), "malformed memory operand");
4226 if (Tok.is(AsmToken::RBrac)) {
4228 Parser.Lex(); // Eat right bracket token.
4230 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4231 0, 0, false, S, E));
4233 // If there's a pre-indexing writeback marker, '!', just add it as a token
4234 // operand. It's rather odd, but syntactically valid.
4235 if (Parser.getTok().is(AsmToken::Exclaim)) {
4236 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4237 Parser.Lex(); // Eat the '!'.
4243 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4244 Parser.Lex(); // Eat the comma.
4246 // If we have a ':', it's an alignment specifier.
4247 if (Parser.getTok().is(AsmToken::Colon)) {
4248 Parser.Lex(); // Eat the ':'.
4249 E = Parser.getTok().getLoc();
4252 if (getParser().ParseExpression(Expr))
4255 // The expression has to be a constant. Memory references with relocations
4256 // don't come through here, as they use the <label> forms of the relevant
4258 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4260 return Error (E, "constant expression expected");
4263 switch (CE->getValue()) {
4266 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4267 case 16: Align = 2; break;
4268 case 32: Align = 4; break;
4269 case 64: Align = 8; break;
4270 case 128: Align = 16; break;
4271 case 256: Align = 32; break;
4274 // Now we should have the closing ']'
4275 E = Parser.getTok().getLoc();
4276 if (Parser.getTok().isNot(AsmToken::RBrac))
4277 return Error(E, "']' expected");
4278 Parser.Lex(); // Eat right bracket token.
4280 // Don't worry about range checking the value here. That's handled by
4281 // the is*() predicates.
4282 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4283 ARM_AM::no_shift, 0, Align,
4286 // If there's a pre-indexing writeback marker, '!', just add it as a token
4288 if (Parser.getTok().is(AsmToken::Exclaim)) {
4289 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4290 Parser.Lex(); // Eat the '!'.
4296 // If we have a '#', it's an immediate offset, else assume it's a register
4297 // offset. Be friendly and also accept a plain integer (without a leading
4298 // hash) for gas compatibility.
4299 if (Parser.getTok().is(AsmToken::Hash) ||
4300 Parser.getTok().is(AsmToken::Dollar) ||
4301 Parser.getTok().is(AsmToken::Integer)) {
4302 if (Parser.getTok().isNot(AsmToken::Integer))
4303 Parser.Lex(); // Eat the '#'.
4304 E = Parser.getTok().getLoc();
4306 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4307 const MCExpr *Offset;
4308 if (getParser().ParseExpression(Offset))
4311 // The expression has to be a constant. Memory references with relocations
4312 // don't come through here, as they use the <label> forms of the relevant
4314 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4316 return Error (E, "constant expression expected");
4318 // If the constant was #-0, represent it as INT32_MIN.
4319 int32_t Val = CE->getValue();
4320 if (isNegative && Val == 0)
4321 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4323 // Now we should have the closing ']'
4324 E = Parser.getTok().getLoc();
4325 if (Parser.getTok().isNot(AsmToken::RBrac))
4326 return Error(E, "']' expected");
4327 Parser.Lex(); // Eat right bracket token.
4329 // Don't worry about range checking the value here. That's handled by
4330 // the is*() predicates.
4331 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4332 ARM_AM::no_shift, 0, 0,
4335 // If there's a pre-indexing writeback marker, '!', just add it as a token
4337 if (Parser.getTok().is(AsmToken::Exclaim)) {
4338 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4339 Parser.Lex(); // Eat the '!'.
4345 // The register offset is optionally preceded by a '+' or '-'
4346 bool isNegative = false;
4347 if (Parser.getTok().is(AsmToken::Minus)) {
4349 Parser.Lex(); // Eat the '-'.
4350 } else if (Parser.getTok().is(AsmToken::Plus)) {
4352 Parser.Lex(); // Eat the '+'.
4355 E = Parser.getTok().getLoc();
4356 int OffsetRegNum = tryParseRegister();
4357 if (OffsetRegNum == -1)
4358 return Error(E, "register expected");
4360 // If there's a shift operator, handle it.
4361 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4362 unsigned ShiftImm = 0;
4363 if (Parser.getTok().is(AsmToken::Comma)) {
4364 Parser.Lex(); // Eat the ','.
4365 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4369 // Now we should have the closing ']'
4370 E = Parser.getTok().getLoc();
4371 if (Parser.getTok().isNot(AsmToken::RBrac))
4372 return Error(E, "']' expected");
4373 Parser.Lex(); // Eat right bracket token.
4375 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4376 ShiftType, ShiftImm, 0, isNegative,
4379 // If there's a pre-indexing writeback marker, '!', just add it as a token
4381 if (Parser.getTok().is(AsmToken::Exclaim)) {
4382 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4383 Parser.Lex(); // Eat the '!'.
4389 /// parseMemRegOffsetShift - one of these two:
4390 /// ( lsl | lsr | asr | ror ) , # shift_amount
4392 /// return true if it parses a shift otherwise it returns false.
4393 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4395 SMLoc Loc = Parser.getTok().getLoc();
4396 const AsmToken &Tok = Parser.getTok();
4397 if (Tok.isNot(AsmToken::Identifier))
4399 StringRef ShiftName = Tok.getString();
4400 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4401 ShiftName == "asl" || ShiftName == "ASL")
4403 else if (ShiftName == "lsr" || ShiftName == "LSR")
4405 else if (ShiftName == "asr" || ShiftName == "ASR")
4407 else if (ShiftName == "ror" || ShiftName == "ROR")
4409 else if (ShiftName == "rrx" || ShiftName == "RRX")
4412 return Error(Loc, "illegal shift operator");
4413 Parser.Lex(); // Eat shift type token.
4415 // rrx stands alone.
4417 if (St != ARM_AM::rrx) {
4418 Loc = Parser.getTok().getLoc();
4419 // A '#' and a shift amount.
4420 const AsmToken &HashTok = Parser.getTok();
4421 if (HashTok.isNot(AsmToken::Hash) &&
4422 HashTok.isNot(AsmToken::Dollar))
4423 return Error(HashTok.getLoc(), "'#' expected");
4424 Parser.Lex(); // Eat hash token.
4427 if (getParser().ParseExpression(Expr))
4429 // Range check the immediate.
4430 // lsl, ror: 0 <= imm <= 31
4431 // lsr, asr: 0 <= imm <= 32
4432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4434 return Error(Loc, "shift amount must be an immediate");
4435 int64_t Imm = CE->getValue();
4437 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4438 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4439 return Error(Loc, "immediate shift value out of range");
4440 // If <ShiftTy> #0, turn it into a no_shift.
4443 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4452 /// parseFPImm - A floating point immediate expression operand.
4453 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4454 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4455 // Anything that can accept a floating point constant as an operand
4456 // needs to go through here, as the regular ParseExpression is
4459 // This routine still creates a generic Immediate operand, containing
4460 // a bitcast of the 64-bit floating point value. The various operands
4461 // that accept floats can check whether the value is valid for them
4462 // via the standard is*() predicates.
4464 SMLoc S = Parser.getTok().getLoc();
4466 if (Parser.getTok().isNot(AsmToken::Hash) &&
4467 Parser.getTok().isNot(AsmToken::Dollar))
4468 return MatchOperand_NoMatch;
4470 // Disambiguate the VMOV forms that can accept an FP immediate.
4471 // vmov.f32 <sreg>, #imm
4472 // vmov.f64 <dreg>, #imm
4473 // vmov.f32 <dreg>, #imm @ vector f32x2
4474 // vmov.f32 <qreg>, #imm @ vector f32x4
4476 // There are also the NEON VMOV instructions which expect an
4477 // integer constant. Make sure we don't try to parse an FPImm
4479 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4480 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4481 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4482 TyOp->getToken() != ".f64"))
4483 return MatchOperand_NoMatch;
4485 Parser.Lex(); // Eat the '#'.
4487 // Handle negation, as that still comes through as a separate token.
4488 bool isNegative = false;
4489 if (Parser.getTok().is(AsmToken::Minus)) {
4493 const AsmToken &Tok = Parser.getTok();
4494 SMLoc Loc = Tok.getLoc();
4495 if (Tok.is(AsmToken::Real)) {
4496 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4497 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4498 // If we had a '-' in front, toggle the sign bit.
4499 IntVal ^= (uint64_t)isNegative << 31;
4500 Parser.Lex(); // Eat the token.
4501 Operands.push_back(ARMOperand::CreateImm(
4502 MCConstantExpr::Create(IntVal, getContext()),
4503 S, Parser.getTok().getLoc()));
4504 return MatchOperand_Success;
4506 // Also handle plain integers. Instructions which allow floating point
4507 // immediates also allow a raw encoded 8-bit value.
4508 if (Tok.is(AsmToken::Integer)) {
4509 int64_t Val = Tok.getIntVal();
4510 Parser.Lex(); // Eat the token.
4511 if (Val > 255 || Val < 0) {
4512 Error(Loc, "encoded floating point value out of range");
4513 return MatchOperand_ParseFail;
4515 double RealVal = ARM_AM::getFPImmFloat(Val);
4516 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4517 Operands.push_back(ARMOperand::CreateImm(
4518 MCConstantExpr::Create(Val, getContext()), S,
4519 Parser.getTok().getLoc()));
4520 return MatchOperand_Success;
4523 Error(Loc, "invalid floating point immediate");
4524 return MatchOperand_ParseFail;
4527 /// Parse a arm instruction operand. For now this parses the operand regardless
4528 /// of the mnemonic.
4529 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4530 StringRef Mnemonic) {
4533 // Check if the current operand has a custom associated parser, if so, try to
4534 // custom parse the operand, or fallback to the general approach.
4535 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4536 if (ResTy == MatchOperand_Success)
4538 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4539 // there was a match, but an error occurred, in which case, just return that
4540 // the operand parsing failed.
4541 if (ResTy == MatchOperand_ParseFail)
4544 switch (getLexer().getKind()) {
4546 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4548 case AsmToken::Identifier: {
4549 if (!tryParseRegisterWithWriteBack(Operands))
4551 int Res = tryParseShiftRegister(Operands);
4552 if (Res == 0) // success
4554 else if (Res == -1) // irrecoverable error
4556 // If this is VMRS, check for the apsr_nzcv operand.
4557 if (Mnemonic == "vmrs" &&
4558 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4559 S = Parser.getTok().getLoc();
4561 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4565 // Fall though for the Identifier case that is not a register or a
4568 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4569 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4570 case AsmToken::String: // quoted label names.
4571 case AsmToken::Dot: { // . as a branch target
4572 // This was not a register so parse other operands that start with an
4573 // identifier (like labels) as expressions and create them as immediates.
4574 const MCExpr *IdVal;
4575 S = Parser.getTok().getLoc();
4576 if (getParser().ParseExpression(IdVal))
4578 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4579 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4582 case AsmToken::LBrac:
4583 return parseMemory(Operands);
4584 case AsmToken::LCurly:
4585 return parseRegisterList(Operands);
4586 case AsmToken::Dollar:
4587 case AsmToken::Hash: {
4588 // #42 -> immediate.
4589 S = Parser.getTok().getLoc();
4592 if (Parser.getTok().isNot(AsmToken::Colon)) {
4593 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4594 const MCExpr *ImmVal;
4595 if (getParser().ParseExpression(ImmVal))
4597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4599 int32_t Val = CE->getValue();
4600 if (isNegative && Val == 0)
4601 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4603 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4604 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4607 // w/ a ':' after the '#', it's just like a plain ':'.
4610 case AsmToken::Colon: {
4611 // ":lower16:" and ":upper16:" expression prefixes
4612 // FIXME: Check it's an expression prefix,
4613 // e.g. (FOO - :lower16:BAR) isn't legal.
4614 ARMMCExpr::VariantKind RefKind;
4615 if (parsePrefix(RefKind))
4618 const MCExpr *SubExprVal;
4619 if (getParser().ParseExpression(SubExprVal))
4622 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4624 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4625 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4631 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4632 // :lower16: and :upper16:.
4633 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4634 RefKind = ARMMCExpr::VK_ARM_None;
4636 // :lower16: and :upper16: modifiers
4637 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4638 Parser.Lex(); // Eat ':'
4640 if (getLexer().isNot(AsmToken::Identifier)) {
4641 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4645 StringRef IDVal = Parser.getTok().getIdentifier();
4646 if (IDVal == "lower16") {
4647 RefKind = ARMMCExpr::VK_ARM_LO16;
4648 } else if (IDVal == "upper16") {
4649 RefKind = ARMMCExpr::VK_ARM_HI16;
4651 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4656 if (getLexer().isNot(AsmToken::Colon)) {
4657 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4660 Parser.Lex(); // Eat the last ':'
4664 /// \brief Given a mnemonic, split out possible predication code and carry
4665 /// setting letters to form a canonical mnemonic and flags.
4667 // FIXME: Would be nice to autogen this.
4668 // FIXME: This is a bit of a maze of special cases.
4669 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4670 unsigned &PredicationCode,
4672 unsigned &ProcessorIMod,
4673 StringRef &ITMask) {
4674 PredicationCode = ARMCC::AL;
4675 CarrySetting = false;
4678 // Ignore some mnemonics we know aren't predicated forms.
4680 // FIXME: Would be nice to autogen this.
4681 if ((Mnemonic == "movs" && isThumb()) ||
4682 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4683 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4684 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4685 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4686 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4687 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4688 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4689 Mnemonic == "fmuls")
4692 // First, split out any predication code. Ignore mnemonics we know aren't
4693 // predicated but do have a carry-set and so weren't caught above.
4694 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4695 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4696 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4697 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4698 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4699 .Case("eq", ARMCC::EQ)
4700 .Case("ne", ARMCC::NE)
4701 .Case("hs", ARMCC::HS)
4702 .Case("cs", ARMCC::HS)
4703 .Case("lo", ARMCC::LO)
4704 .Case("cc", ARMCC::LO)
4705 .Case("mi", ARMCC::MI)
4706 .Case("pl", ARMCC::PL)
4707 .Case("vs", ARMCC::VS)
4708 .Case("vc", ARMCC::VC)
4709 .Case("hi", ARMCC::HI)
4710 .Case("ls", ARMCC::LS)
4711 .Case("ge", ARMCC::GE)
4712 .Case("lt", ARMCC::LT)
4713 .Case("gt", ARMCC::GT)
4714 .Case("le", ARMCC::LE)
4715 .Case("al", ARMCC::AL)
4718 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4719 PredicationCode = CC;
4723 // Next, determine if we have a carry setting bit. We explicitly ignore all
4724 // the instructions we know end in 's'.
4725 if (Mnemonic.endswith("s") &&
4726 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4727 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4728 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4729 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4730 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4731 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4732 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4733 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4734 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4735 (Mnemonic == "movs" && isThumb()))) {
4736 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4737 CarrySetting = true;
4740 // The "cps" instruction can have a interrupt mode operand which is glued into
4741 // the mnemonic. Check if this is the case, split it and parse the imod op
4742 if (Mnemonic.startswith("cps")) {
4743 // Split out any imod code.
4745 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4746 .Case("ie", ARM_PROC::IE)
4747 .Case("id", ARM_PROC::ID)
4750 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4751 ProcessorIMod = IMod;
4755 // The "it" instruction has the condition mask on the end of the mnemonic.
4756 if (Mnemonic.startswith("it")) {
4757 ITMask = Mnemonic.slice(2, Mnemonic.size());
4758 Mnemonic = Mnemonic.slice(0, 2);
4764 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4765 /// inclusion of carry set or predication code operands.
4767 // FIXME: It would be nice to autogen this.
4769 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4770 bool &CanAcceptPredicationCode) {
4771 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4772 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4773 Mnemonic == "add" || Mnemonic == "adc" ||
4774 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4775 Mnemonic == "orr" || Mnemonic == "mvn" ||
4776 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4777 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4778 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4779 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4780 Mnemonic == "mla" || Mnemonic == "smlal" ||
4781 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4782 CanAcceptCarrySet = true;
4784 CanAcceptCarrySet = false;
4786 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4787 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4788 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4789 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4790 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4791 (Mnemonic == "clrex" && !isThumb()) ||
4792 (Mnemonic == "nop" && isThumbOne()) ||
4793 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4794 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4795 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4796 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4798 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4799 CanAcceptPredicationCode = false;
4801 CanAcceptPredicationCode = true;
4804 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4805 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4806 CanAcceptPredicationCode = false;
4810 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4811 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4812 // FIXME: This is all horribly hacky. We really need a better way to deal
4813 // with optional operands like this in the matcher table.
4815 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4816 // another does not. Specifically, the MOVW instruction does not. So we
4817 // special case it here and remove the defaulted (non-setting) cc_out
4818 // operand if that's the instruction we're trying to match.
4820 // We do this as post-processing of the explicit operands rather than just
4821 // conditionally adding the cc_out in the first place because we need
4822 // to check the type of the parsed immediate operand.
4823 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4824 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4825 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4826 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4829 // Register-register 'add' for thumb does not have a cc_out operand
4830 // when there are only two register operands.
4831 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4832 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4833 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4834 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4836 // Register-register 'add' for thumb does not have a cc_out operand
4837 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4838 // have to check the immediate range here since Thumb2 has a variant
4839 // that can handle a different range and has a cc_out operand.
4840 if (((isThumb() && Mnemonic == "add") ||
4841 (isThumbTwo() && Mnemonic == "sub")) &&
4842 Operands.size() == 6 &&
4843 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4844 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4845 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4846 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4847 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4848 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4850 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4851 // imm0_4095 variant. That's the least-preferred variant when
4852 // selecting via the generic "add" mnemonic, so to know that we
4853 // should remove the cc_out operand, we have to explicitly check that
4854 // it's not one of the other variants. Ugh.
4855 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4856 Operands.size() == 6 &&
4857 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4858 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4859 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4860 // Nest conditions rather than one big 'if' statement for readability.
4862 // If either register is a high reg, it's either one of the SP
4863 // variants (handled above) or a 32-bit encoding, so we just
4864 // check against T3. If the second register is the PC, this is an
4865 // alternate form of ADR, which uses encoding T4, so check for that too.
4866 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4867 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4868 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4869 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4871 // If both registers are low, we're in an IT block, and the immediate is
4872 // in range, we should use encoding T1 instead, which has a cc_out.
4874 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4875 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4876 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4879 // Otherwise, we use encoding T4, which does not have a cc_out
4884 // The thumb2 multiply instruction doesn't have a CCOut register, so
4885 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4886 // use the 16-bit encoding or not.
4887 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4888 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4889 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4890 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4891 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4892 // If the registers aren't low regs, the destination reg isn't the
4893 // same as one of the source regs, or the cc_out operand is zero
4894 // outside of an IT block, we have to use the 32-bit encoding, so
4895 // remove the cc_out operand.
4896 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4897 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4898 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4900 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4901 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4902 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4903 static_cast<ARMOperand*>(Operands[4])->getReg())))
4906 // Also check the 'mul' syntax variant that doesn't specify an explicit
4907 // destination register.
4908 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4909 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4910 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4911 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4912 // If the registers aren't low regs or the cc_out operand is zero
4913 // outside of an IT block, we have to use the 32-bit encoding, so
4914 // remove the cc_out operand.
4915 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4916 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4922 // Register-register 'add/sub' for thumb does not have a cc_out operand
4923 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4924 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4925 // right, this will result in better diagnostics (which operand is off)
4927 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4928 (Operands.size() == 5 || Operands.size() == 6) &&
4929 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4930 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4931 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4932 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4933 (Operands.size() == 6 &&
4934 static_cast<ARMOperand*>(Operands[5])->isImm())))
4940 static bool isDataTypeToken(StringRef Tok) {
4941 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4942 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4943 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4944 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4945 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4946 Tok == ".f" || Tok == ".d";
4949 // FIXME: This bit should probably be handled via an explicit match class
4950 // in the .td files that matches the suffix instead of having it be
4951 // a literal string token the way it is now.
4952 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4953 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4956 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4957 /// Parse an arm instruction mnemonic followed by its operands.
4958 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4960 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4961 // Apply mnemonic aliases before doing anything else, as the destination
4962 // mnemnonic may include suffices and we want to handle them normally.
4963 // The generic tblgen'erated code does this later, at the start of
4964 // MatchInstructionImpl(), but that's too late for aliases that include
4965 // any sort of suffix.
4966 unsigned AvailableFeatures = getAvailableFeatures();
4967 applyMnemonicAliases(Name, AvailableFeatures);
4969 // First check for the ARM-specific .req directive.
4970 if (Parser.getTok().is(AsmToken::Identifier) &&
4971 Parser.getTok().getIdentifier() == ".req") {
4972 parseDirectiveReq(Name, NameLoc);
4973 // We always return 'error' for this, as we're done with this
4974 // statement and don't need to match the 'instruction."
4978 // Create the leading tokens for the mnemonic, split by '.' characters.
4979 size_t Start = 0, Next = Name.find('.');
4980 StringRef Mnemonic = Name.slice(Start, Next);
4982 // Split out the predication code and carry setting flag from the mnemonic.
4983 unsigned PredicationCode;
4984 unsigned ProcessorIMod;
4987 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4988 ProcessorIMod, ITMask);
4990 // In Thumb1, only the branch (B) instruction can be predicated.
4991 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4992 Parser.EatToEndOfStatement();
4993 return Error(NameLoc, "conditional execution not supported in Thumb1");
4996 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4998 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4999 // is the mask as it will be for the IT encoding if the conditional
5000 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5001 // where the conditional bit0 is zero, the instruction post-processing
5002 // will adjust the mask accordingly.
5003 if (Mnemonic == "it") {
5004 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5005 if (ITMask.size() > 3) {
5006 Parser.EatToEndOfStatement();
5007 return Error(Loc, "too many conditions on IT instruction");
5010 for (unsigned i = ITMask.size(); i != 0; --i) {
5011 char pos = ITMask[i - 1];
5012 if (pos != 't' && pos != 'e') {
5013 Parser.EatToEndOfStatement();
5014 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5017 if (ITMask[i - 1] == 't')
5020 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5023 // FIXME: This is all a pretty gross hack. We should automatically handle
5024 // optional operands like this via tblgen.
5026 // Next, add the CCOut and ConditionCode operands, if needed.
5028 // For mnemonics which can ever incorporate a carry setting bit or predication
5029 // code, our matching model involves us always generating CCOut and
5030 // ConditionCode operands to match the mnemonic "as written" and then we let
5031 // the matcher deal with finding the right instruction or generating an
5032 // appropriate error.
5033 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5034 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5036 // If we had a carry-set on an instruction that can't do that, issue an
5038 if (!CanAcceptCarrySet && CarrySetting) {
5039 Parser.EatToEndOfStatement();
5040 return Error(NameLoc, "instruction '" + Mnemonic +
5041 "' can not set flags, but 's' suffix specified");
5043 // If we had a predication code on an instruction that can't do that, issue an
5045 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5046 Parser.EatToEndOfStatement();
5047 return Error(NameLoc, "instruction '" + Mnemonic +
5048 "' is not predicable, but condition code specified");
5051 // Add the carry setting operand, if necessary.
5052 if (CanAcceptCarrySet) {
5053 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5054 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5058 // Add the predication code operand, if necessary.
5059 if (CanAcceptPredicationCode) {
5060 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5062 Operands.push_back(ARMOperand::CreateCondCode(
5063 ARMCC::CondCodes(PredicationCode), Loc));
5066 // Add the processor imod operand, if necessary.
5067 if (ProcessorIMod) {
5068 Operands.push_back(ARMOperand::CreateImm(
5069 MCConstantExpr::Create(ProcessorIMod, getContext()),
5073 // Add the remaining tokens in the mnemonic.
5074 while (Next != StringRef::npos) {
5076 Next = Name.find('.', Start + 1);
5077 StringRef ExtraToken = Name.slice(Start, Next);
5079 // Some NEON instructions have an optional datatype suffix that is
5080 // completely ignored. Check for that.
5081 if (isDataTypeToken(ExtraToken) &&
5082 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5085 if (ExtraToken != ".n") {
5086 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5087 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5091 // Read the remaining operands.
5092 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5093 // Read the first operand.
5094 if (parseOperand(Operands, Mnemonic)) {
5095 Parser.EatToEndOfStatement();
5099 while (getLexer().is(AsmToken::Comma)) {
5100 Parser.Lex(); // Eat the comma.
5102 // Parse and remember the operand.
5103 if (parseOperand(Operands, Mnemonic)) {
5104 Parser.EatToEndOfStatement();
5110 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5111 SMLoc Loc = getLexer().getLoc();
5112 Parser.EatToEndOfStatement();
5113 return Error(Loc, "unexpected token in argument list");
5116 Parser.Lex(); // Consume the EndOfStatement
5118 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5119 // do and don't have a cc_out optional-def operand. With some spot-checks
5120 // of the operand list, we can figure out which variant we're trying to
5121 // parse and adjust accordingly before actually matching. We shouldn't ever
5122 // try to remove a cc_out operand that was explicitly set on the the
5123 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5124 // table driven matcher doesn't fit well with the ARM instruction set.
5125 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5126 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5127 Operands.erase(Operands.begin() + 1);
5131 // ARM mode 'blx' need special handling, as the register operand version
5132 // is predicable, but the label operand version is not. So, we can't rely
5133 // on the Mnemonic based checking to correctly figure out when to put
5134 // a k_CondCode operand in the list. If we're trying to match the label
5135 // version, remove the k_CondCode operand here.
5136 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5137 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5138 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5139 Operands.erase(Operands.begin() + 1);
5143 // The vector-compare-to-zero instructions have a literal token "#0" at
5144 // the end that comes to here as an immediate operand. Convert it to a
5145 // token to play nicely with the matcher.
5146 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5147 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5148 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5149 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5150 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5151 if (CE && CE->getValue() == 0) {
5152 Operands.erase(Operands.begin() + 5);
5153 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5157 // VCMP{E} does the same thing, but with a different operand count.
5158 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5159 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5160 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5161 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5162 if (CE && CE->getValue() == 0) {
5163 Operands.erase(Operands.begin() + 4);
5164 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5168 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5169 // end. Convert it to a token here. Take care not to convert those
5170 // that should hit the Thumb2 encoding.
5171 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5172 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5173 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5174 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5175 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5177 if (CE && CE->getValue() == 0 &&
5179 // The cc_out operand matches the IT block.
5180 ((inITBlock() != CarrySetting) &&
5181 // Neither register operand is a high register.
5182 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5183 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5184 Operands.erase(Operands.begin() + 5);
5185 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5190 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5191 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5192 // a single GPRPair reg operand is used in the .td file to replace the two
5193 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5194 // expressed as a GPRPair, so we have to manually merge them.
5195 // FIXME: We would really like to be able to tablegen'erate this.
5196 if (!isThumb() && Operands.size() > 4 &&
5197 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5198 bool isLoad = (Mnemonic == "ldrexd");
5199 unsigned Idx = isLoad ? 2 : 3;
5200 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5201 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5203 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5204 // Adjust only if Op1 and Op2 are GPRs.
5205 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5206 MRC.contains(Op2->getReg())) {
5207 unsigned Reg1 = Op1->getReg();
5208 unsigned Reg2 = Op2->getReg();
5209 unsigned Rt = MRI->getEncodingValue(Reg1);
5210 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5212 // Rt2 must be Rt + 1 and Rt must be even.
5213 if (Rt + 1 != Rt2 || (Rt & 1)) {
5214 Error(Op2->getStartLoc(), isLoad ?
5215 "destination operands must be sequential" :
5216 "source operands must be sequential");
5219 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5220 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5221 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5222 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5223 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5232 // Validate context-sensitive operand constraints.
5234 // return 'true' if register list contains non-low GPR registers,
5235 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5236 // 'containsReg' to true.
5237 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5238 unsigned HiReg, bool &containsReg) {
5239 containsReg = false;
5240 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5241 unsigned OpReg = Inst.getOperand(i).getReg();
5244 // Anything other than a low register isn't legal here.
5245 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5251 // Check if the specified regisgter is in the register list of the inst,
5252 // starting at the indicated operand number.
5253 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5254 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5255 unsigned OpReg = Inst.getOperand(i).getReg();
5262 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5263 // the ARMInsts array) instead. Getting that here requires awkward
5264 // API changes, though. Better way?
5266 extern const MCInstrDesc ARMInsts[];
5268 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5269 return ARMInsts[Opcode];
5272 // FIXME: We would really like to be able to tablegen'erate this.
5274 validateInstruction(MCInst &Inst,
5275 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5276 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5277 SMLoc Loc = Operands[0]->getStartLoc();
5278 // Check the IT block state first.
5279 // NOTE: BKPT instruction has the interesting property of being
5280 // allowed in IT blocks, but not being predicable. It just always
5282 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5283 Inst.getOpcode() != ARM::BKPT) {
5285 if (ITState.FirstCond)
5286 ITState.FirstCond = false;
5288 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5289 // The instruction must be predicable.
5290 if (!MCID.isPredicable())
5291 return Error(Loc, "instructions in IT block must be predicable");
5292 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5293 unsigned ITCond = bit ? ITState.Cond :
5294 ARMCC::getOppositeCondition(ITState.Cond);
5295 if (Cond != ITCond) {
5296 // Find the condition code Operand to get its SMLoc information.
5298 for (unsigned i = 1; i < Operands.size(); ++i)
5299 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5300 CondLoc = Operands[i]->getStartLoc();
5301 return Error(CondLoc, "incorrect condition in IT block; got '" +
5302 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5303 "', but expected '" +
5304 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5306 // Check for non-'al' condition codes outside of the IT block.
5307 } else if (isThumbTwo() && MCID.isPredicable() &&
5308 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5309 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5310 Inst.getOpcode() != ARM::t2B)
5311 return Error(Loc, "predicated instructions must be in IT block");
5313 switch (Inst.getOpcode()) {
5316 case ARM::LDRD_POST: {
5317 // Rt2 must be Rt + 1.
5318 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5319 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5321 return Error(Operands[3]->getStartLoc(),
5322 "destination operands must be sequential");
5326 // Rt2 must be Rt + 1.
5327 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5328 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5330 return Error(Operands[3]->getStartLoc(),
5331 "source operands must be sequential");
5335 case ARM::STRD_POST: {
5336 // Rt2 must be Rt + 1.
5337 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5338 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5340 return Error(Operands[3]->getStartLoc(),
5341 "source operands must be sequential");
5346 // width must be in range [1, 32-lsb]
5347 unsigned lsb = Inst.getOperand(2).getImm();
5348 unsigned widthm1 = Inst.getOperand(3).getImm();
5349 if (widthm1 >= 32 - lsb)
5350 return Error(Operands[5]->getStartLoc(),
5351 "bitfield width must be in range [1,32-lsb]");
5355 // If we're parsing Thumb2, the .w variant is available and handles
5356 // most cases that are normally illegal for a Thumb1 LDM
5357 // instruction. We'll make the transformation in processInstruction()
5360 // Thumb LDM instructions are writeback iff the base register is not
5361 // in the register list.
5362 unsigned Rn = Inst.getOperand(0).getReg();
5363 bool hasWritebackToken =
5364 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5365 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5366 bool listContainsBase;
5367 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5368 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5369 "registers must be in range r0-r7");
5370 // If we should have writeback, then there should be a '!' token.
5371 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5372 return Error(Operands[2]->getStartLoc(),
5373 "writeback operator '!' expected");
5374 // If we should not have writeback, there must not be a '!'. This is
5375 // true even for the 32-bit wide encodings.
5376 if (listContainsBase && hasWritebackToken)
5377 return Error(Operands[3]->getStartLoc(),
5378 "writeback operator '!' not allowed when base register "
5379 "in register list");
5383 case ARM::t2LDMIA_UPD: {
5384 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5385 return Error(Operands[4]->getStartLoc(),
5386 "writeback operator '!' not allowed when base register "
5387 "in register list");
5391 // The second source operand must be the same register as the destination
5394 // In this case, we must directly check the parsed operands because the
5395 // cvtThumbMultiply() function is written in such a way that it guarantees
5396 // this first statement is always true for the new Inst. Essentially, the
5397 // destination is unconditionally copied into the second source operand
5398 // without checking to see if it matches what we actually parsed.
5399 if (Operands.size() == 6 &&
5400 (((ARMOperand*)Operands[3])->getReg() !=
5401 ((ARMOperand*)Operands[5])->getReg()) &&
5402 (((ARMOperand*)Operands[3])->getReg() !=
5403 ((ARMOperand*)Operands[4])->getReg())) {
5404 return Error(Operands[3]->getStartLoc(),
5405 "destination register must match source register");
5409 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5410 // so only issue a diagnostic for thumb1. The instructions will be
5411 // switched to the t2 encodings in processInstruction() if necessary.
5413 bool listContainsBase;
5414 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5416 return Error(Operands[2]->getStartLoc(),
5417 "registers must be in range r0-r7 or pc");
5421 bool listContainsBase;
5422 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5424 return Error(Operands[2]->getStartLoc(),
5425 "registers must be in range r0-r7 or lr");
5428 case ARM::tSTMIA_UPD: {
5429 bool listContainsBase;
5430 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5431 return Error(Operands[4]->getStartLoc(),
5432 "registers must be in range r0-r7");
5435 case ARM::tADDrSP: {
5436 // If the non-SP source operand and the destination operand are not the
5437 // same, we need thumb2 (for the wide encoding), or we have an error.
5438 if (!isThumbTwo() &&
5439 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5440 return Error(Operands[4]->getStartLoc(),
5441 "source register must be the same as destination");
5450 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5452 default: llvm_unreachable("unexpected opcode!");
5454 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5455 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5456 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5457 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5458 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5459 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5460 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5461 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5462 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5465 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5466 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5467 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5468 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5469 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5471 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5472 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5473 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5474 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5475 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5477 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5478 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5479 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5480 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5481 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5484 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5485 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5486 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5487 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5488 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5489 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5490 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5491 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5492 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5493 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5494 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5495 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5496 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5497 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5498 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5501 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5502 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5503 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5504 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5505 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5506 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5507 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5508 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5509 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5510 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5511 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5512 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5513 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5514 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5515 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5516 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5517 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5518 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5521 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5522 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5523 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5524 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5525 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5526 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5527 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5528 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5529 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5530 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5531 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5532 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5533 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5534 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5535 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5538 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5539 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5540 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5541 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5542 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5543 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5544 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5545 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5546 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5547 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5548 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5549 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5550 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5551 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5552 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5553 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5554 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5555 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5559 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5561 default: llvm_unreachable("unexpected opcode!");
5563 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5564 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5565 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5566 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5567 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5568 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5569 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5570 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5571 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5574 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5575 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5576 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5577 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5578 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5579 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5580 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5581 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5582 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5583 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5584 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5585 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5586 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5587 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5588 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5591 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5592 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5593 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5594 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5595 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5596 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5597 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5598 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5599 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5600 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5601 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5602 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5603 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5604 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5605 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5606 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5607 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5608 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5611 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5612 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5613 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5614 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5615 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5616 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5617 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5618 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5619 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5620 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5621 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5622 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5623 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5624 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5625 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5628 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5629 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5630 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5631 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5632 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5633 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5634 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5635 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5636 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5637 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5638 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5639 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5640 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5641 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5642 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5643 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5644 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5645 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5648 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5649 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5650 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5651 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5652 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5653 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5654 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5655 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5656 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5657 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5658 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5659 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5660 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5661 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5662 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5665 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5666 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5667 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5668 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5669 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5670 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5671 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5672 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5673 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5674 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5675 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5676 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5677 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5678 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5679 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5680 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5681 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5682 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5685 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5686 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5687 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5688 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5689 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5690 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5691 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5692 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5693 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5694 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5695 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5696 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5697 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5698 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5699 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5700 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5701 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5702 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5707 processInstruction(MCInst &Inst,
5708 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5709 switch (Inst.getOpcode()) {
5710 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5712 if (Inst.getOperand(1).getReg() != ARM::PC ||
5713 Inst.getOperand(5).getReg() != 0)
5716 TmpInst.setOpcode(ARM::ADR);
5717 TmpInst.addOperand(Inst.getOperand(0));
5718 TmpInst.addOperand(Inst.getOperand(2));
5719 TmpInst.addOperand(Inst.getOperand(3));
5720 TmpInst.addOperand(Inst.getOperand(4));
5724 // Aliases for alternate PC+imm syntax of LDR instructions.
5725 case ARM::t2LDRpcrel:
5726 Inst.setOpcode(ARM::t2LDRpci);
5728 case ARM::t2LDRBpcrel:
5729 Inst.setOpcode(ARM::t2LDRBpci);
5731 case ARM::t2LDRHpcrel:
5732 Inst.setOpcode(ARM::t2LDRHpci);
5734 case ARM::t2LDRSBpcrel:
5735 Inst.setOpcode(ARM::t2LDRSBpci);
5737 case ARM::t2LDRSHpcrel:
5738 Inst.setOpcode(ARM::t2LDRSHpci);
5740 // Handle NEON VST complex aliases.
5741 case ARM::VST1LNdWB_register_Asm_8:
5742 case ARM::VST1LNdWB_register_Asm_16:
5743 case ARM::VST1LNdWB_register_Asm_32: {
5745 // Shuffle the operands around so the lane index operand is in the
5748 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5749 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5750 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5751 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5752 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5753 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5754 TmpInst.addOperand(Inst.getOperand(1)); // lane
5755 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5756 TmpInst.addOperand(Inst.getOperand(6));
5761 case ARM::VST2LNdWB_register_Asm_8:
5762 case ARM::VST2LNdWB_register_Asm_16:
5763 case ARM::VST2LNdWB_register_Asm_32:
5764 case ARM::VST2LNqWB_register_Asm_16:
5765 case ARM::VST2LNqWB_register_Asm_32: {
5767 // Shuffle the operands around so the lane index operand is in the
5770 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5771 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5772 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5773 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5774 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5775 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5776 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5778 TmpInst.addOperand(Inst.getOperand(1)); // lane
5779 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5780 TmpInst.addOperand(Inst.getOperand(6));
5785 case ARM::VST3LNdWB_register_Asm_8:
5786 case ARM::VST3LNdWB_register_Asm_16:
5787 case ARM::VST3LNdWB_register_Asm_32:
5788 case ARM::VST3LNqWB_register_Asm_16:
5789 case ARM::VST3LNqWB_register_Asm_32: {
5791 // Shuffle the operands around so the lane index operand is in the
5794 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5795 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5796 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5797 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5798 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5799 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5800 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5802 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5804 TmpInst.addOperand(Inst.getOperand(1)); // lane
5805 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5806 TmpInst.addOperand(Inst.getOperand(6));
5811 case ARM::VST4LNdWB_register_Asm_8:
5812 case ARM::VST4LNdWB_register_Asm_16:
5813 case ARM::VST4LNdWB_register_Asm_32:
5814 case ARM::VST4LNqWB_register_Asm_16:
5815 case ARM::VST4LNqWB_register_Asm_32: {
5817 // Shuffle the operands around so the lane index operand is in the
5820 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5821 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5822 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5823 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5824 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5825 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5826 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5832 TmpInst.addOperand(Inst.getOperand(1)); // lane
5833 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5834 TmpInst.addOperand(Inst.getOperand(6));
5839 case ARM::VST1LNdWB_fixed_Asm_8:
5840 case ARM::VST1LNdWB_fixed_Asm_16:
5841 case ARM::VST1LNdWB_fixed_Asm_32: {
5843 // Shuffle the operands around so the lane index operand is in the
5846 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5847 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5848 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5849 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5850 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5851 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5852 TmpInst.addOperand(Inst.getOperand(1)); // lane
5853 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5854 TmpInst.addOperand(Inst.getOperand(5));
5859 case ARM::VST2LNdWB_fixed_Asm_8:
5860 case ARM::VST2LNdWB_fixed_Asm_16:
5861 case ARM::VST2LNdWB_fixed_Asm_32:
5862 case ARM::VST2LNqWB_fixed_Asm_16:
5863 case ARM::VST2LNqWB_fixed_Asm_32: {
5865 // Shuffle the operands around so the lane index operand is in the
5868 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5869 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5870 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5871 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5872 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5873 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5874 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5876 TmpInst.addOperand(Inst.getOperand(1)); // lane
5877 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5878 TmpInst.addOperand(Inst.getOperand(5));
5883 case ARM::VST3LNdWB_fixed_Asm_8:
5884 case ARM::VST3LNdWB_fixed_Asm_16:
5885 case ARM::VST3LNdWB_fixed_Asm_32:
5886 case ARM::VST3LNqWB_fixed_Asm_16:
5887 case ARM::VST3LNqWB_fixed_Asm_32: {
5889 // Shuffle the operands around so the lane index operand is in the
5892 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5893 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5894 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5895 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5896 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5897 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5898 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5900 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5902 TmpInst.addOperand(Inst.getOperand(1)); // lane
5903 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5904 TmpInst.addOperand(Inst.getOperand(5));
5909 case ARM::VST4LNdWB_fixed_Asm_8:
5910 case ARM::VST4LNdWB_fixed_Asm_16:
5911 case ARM::VST4LNdWB_fixed_Asm_32:
5912 case ARM::VST4LNqWB_fixed_Asm_16:
5913 case ARM::VST4LNqWB_fixed_Asm_32: {
5915 // Shuffle the operands around so the lane index operand is in the
5918 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5919 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5920 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5921 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5922 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5923 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5924 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5926 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5928 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5930 TmpInst.addOperand(Inst.getOperand(1)); // lane
5931 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5932 TmpInst.addOperand(Inst.getOperand(5));
5937 case ARM::VST1LNdAsm_8:
5938 case ARM::VST1LNdAsm_16:
5939 case ARM::VST1LNdAsm_32: {
5941 // Shuffle the operands around so the lane index operand is in the
5944 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5945 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5946 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5947 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5948 TmpInst.addOperand(Inst.getOperand(1)); // lane
5949 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5950 TmpInst.addOperand(Inst.getOperand(5));
5955 case ARM::VST2LNdAsm_8:
5956 case ARM::VST2LNdAsm_16:
5957 case ARM::VST2LNdAsm_32:
5958 case ARM::VST2LNqAsm_16:
5959 case ARM::VST2LNqAsm_32: {
5961 // Shuffle the operands around so the lane index operand is in the
5964 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5965 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5966 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5967 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5968 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5970 TmpInst.addOperand(Inst.getOperand(1)); // lane
5971 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5972 TmpInst.addOperand(Inst.getOperand(5));
5977 case ARM::VST3LNdAsm_8:
5978 case ARM::VST3LNdAsm_16:
5979 case ARM::VST3LNdAsm_32:
5980 case ARM::VST3LNqAsm_16:
5981 case ARM::VST3LNqAsm_32: {
5983 // Shuffle the operands around so the lane index operand is in the
5986 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5987 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5988 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5989 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5990 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5992 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5994 TmpInst.addOperand(Inst.getOperand(1)); // lane
5995 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5996 TmpInst.addOperand(Inst.getOperand(5));
6001 case ARM::VST4LNdAsm_8:
6002 case ARM::VST4LNdAsm_16:
6003 case ARM::VST4LNdAsm_32:
6004 case ARM::VST4LNqAsm_16:
6005 case ARM::VST4LNqAsm_32: {
6007 // Shuffle the operands around so the lane index operand is in the
6010 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6011 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6012 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6013 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6014 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6016 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6018 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6020 TmpInst.addOperand(Inst.getOperand(1)); // lane
6021 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6022 TmpInst.addOperand(Inst.getOperand(5));
6027 // Handle NEON VLD complex aliases.
6028 case ARM::VLD1LNdWB_register_Asm_8:
6029 case ARM::VLD1LNdWB_register_Asm_16:
6030 case ARM::VLD1LNdWB_register_Asm_32: {
6032 // Shuffle the operands around so the lane index operand is in the
6035 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6036 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6037 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6038 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6039 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6040 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6041 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6042 TmpInst.addOperand(Inst.getOperand(1)); // lane
6043 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6044 TmpInst.addOperand(Inst.getOperand(6));
6049 case ARM::VLD2LNdWB_register_Asm_8:
6050 case ARM::VLD2LNdWB_register_Asm_16:
6051 case ARM::VLD2LNdWB_register_Asm_32:
6052 case ARM::VLD2LNqWB_register_Asm_16:
6053 case ARM::VLD2LNqWB_register_Asm_32: {
6055 // Shuffle the operands around so the lane index operand is in the
6058 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6059 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6060 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6062 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6063 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6064 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6065 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6066 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6067 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6069 TmpInst.addOperand(Inst.getOperand(1)); // lane
6070 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6071 TmpInst.addOperand(Inst.getOperand(6));
6076 case ARM::VLD3LNdWB_register_Asm_8:
6077 case ARM::VLD3LNdWB_register_Asm_16:
6078 case ARM::VLD3LNdWB_register_Asm_32:
6079 case ARM::VLD3LNqWB_register_Asm_16:
6080 case ARM::VLD3LNqWB_register_Asm_32: {
6082 // Shuffle the operands around so the lane index operand is in the
6085 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6086 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6092 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6093 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6094 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6095 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6096 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6098 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6100 TmpInst.addOperand(Inst.getOperand(1)); // lane
6101 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6102 TmpInst.addOperand(Inst.getOperand(6));
6107 case ARM::VLD4LNdWB_register_Asm_8:
6108 case ARM::VLD4LNdWB_register_Asm_16:
6109 case ARM::VLD4LNdWB_register_Asm_32:
6110 case ARM::VLD4LNqWB_register_Asm_16:
6111 case ARM::VLD4LNqWB_register_Asm_32: {
6113 // Shuffle the operands around so the lane index operand is in the
6116 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6117 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6118 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6120 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6122 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6124 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6125 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6126 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6127 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6128 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6129 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6135 TmpInst.addOperand(Inst.getOperand(1)); // lane
6136 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6137 TmpInst.addOperand(Inst.getOperand(6));
6142 case ARM::VLD1LNdWB_fixed_Asm_8:
6143 case ARM::VLD1LNdWB_fixed_Asm_16:
6144 case ARM::VLD1LNdWB_fixed_Asm_32: {
6146 // Shuffle the operands around so the lane index operand is in the
6149 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6150 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6151 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6152 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6153 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6154 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6155 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6156 TmpInst.addOperand(Inst.getOperand(1)); // lane
6157 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6158 TmpInst.addOperand(Inst.getOperand(5));
6163 case ARM::VLD2LNdWB_fixed_Asm_8:
6164 case ARM::VLD2LNdWB_fixed_Asm_16:
6165 case ARM::VLD2LNdWB_fixed_Asm_32:
6166 case ARM::VLD2LNqWB_fixed_Asm_16:
6167 case ARM::VLD2LNqWB_fixed_Asm_32: {
6169 // Shuffle the operands around so the lane index operand is in the
6172 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6173 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6174 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6176 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6177 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6178 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6179 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6180 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6181 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6183 TmpInst.addOperand(Inst.getOperand(1)); // lane
6184 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6185 TmpInst.addOperand(Inst.getOperand(5));
6190 case ARM::VLD3LNdWB_fixed_Asm_8:
6191 case ARM::VLD3LNdWB_fixed_Asm_16:
6192 case ARM::VLD3LNdWB_fixed_Asm_32:
6193 case ARM::VLD3LNqWB_fixed_Asm_16:
6194 case ARM::VLD3LNqWB_fixed_Asm_32: {
6196 // Shuffle the operands around so the lane index operand is in the
6199 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6200 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6201 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6206 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6207 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6208 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6209 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6210 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6212 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6214 TmpInst.addOperand(Inst.getOperand(1)); // lane
6215 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6216 TmpInst.addOperand(Inst.getOperand(5));
6221 case ARM::VLD4LNdWB_fixed_Asm_8:
6222 case ARM::VLD4LNdWB_fixed_Asm_16:
6223 case ARM::VLD4LNdWB_fixed_Asm_32:
6224 case ARM::VLD4LNqWB_fixed_Asm_16:
6225 case ARM::VLD4LNqWB_fixed_Asm_32: {
6227 // Shuffle the operands around so the lane index operand is in the
6230 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6231 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6232 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6239 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6240 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6241 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6242 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6245 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(Inst.getOperand(1)); // lane
6250 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6251 TmpInst.addOperand(Inst.getOperand(5));
6256 case ARM::VLD1LNdAsm_8:
6257 case ARM::VLD1LNdAsm_16:
6258 case ARM::VLD1LNdAsm_32: {
6260 // Shuffle the operands around so the lane index operand is in the
6263 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6264 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6265 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6266 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6267 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6268 TmpInst.addOperand(Inst.getOperand(1)); // lane
6269 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6270 TmpInst.addOperand(Inst.getOperand(5));
6275 case ARM::VLD2LNdAsm_8:
6276 case ARM::VLD2LNdAsm_16:
6277 case ARM::VLD2LNdAsm_32:
6278 case ARM::VLD2LNqAsm_16:
6279 case ARM::VLD2LNqAsm_32: {
6281 // Shuffle the operands around so the lane index operand is in the
6284 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6285 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6288 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6289 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6290 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6291 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6293 TmpInst.addOperand(Inst.getOperand(1)); // lane
6294 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6295 TmpInst.addOperand(Inst.getOperand(5));
6300 case ARM::VLD3LNdAsm_8:
6301 case ARM::VLD3LNdAsm_16:
6302 case ARM::VLD3LNdAsm_32:
6303 case ARM::VLD3LNqAsm_16:
6304 case ARM::VLD3LNqAsm_32: {
6306 // Shuffle the operands around so the lane index operand is in the
6309 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6310 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6311 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6313 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6316 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6317 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6318 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6320 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322 TmpInst.addOperand(Inst.getOperand(1)); // lane
6323 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6324 TmpInst.addOperand(Inst.getOperand(5));
6329 case ARM::VLD4LNdAsm_8:
6330 case ARM::VLD4LNdAsm_16:
6331 case ARM::VLD4LNdAsm_32:
6332 case ARM::VLD4LNqAsm_16:
6333 case ARM::VLD4LNqAsm_32: {
6335 // Shuffle the operands around so the lane index operand is in the
6338 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6339 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6340 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6342 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6346 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6347 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6348 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6349 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6351 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6353 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6355 TmpInst.addOperand(Inst.getOperand(1)); // lane
6356 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6357 TmpInst.addOperand(Inst.getOperand(5));
6362 // VLD3DUP single 3-element structure to all lanes instructions.
6363 case ARM::VLD3DUPdAsm_8:
6364 case ARM::VLD3DUPdAsm_16:
6365 case ARM::VLD3DUPdAsm_32:
6366 case ARM::VLD3DUPqAsm_8:
6367 case ARM::VLD3DUPqAsm_16:
6368 case ARM::VLD3DUPqAsm_32: {
6371 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6372 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6375 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6377 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6378 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6379 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6380 TmpInst.addOperand(Inst.getOperand(4));
6385 case ARM::VLD3DUPdWB_fixed_Asm_8:
6386 case ARM::VLD3DUPdWB_fixed_Asm_16:
6387 case ARM::VLD3DUPdWB_fixed_Asm_32:
6388 case ARM::VLD3DUPqWB_fixed_Asm_8:
6389 case ARM::VLD3DUPqWB_fixed_Asm_16:
6390 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6393 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6394 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6397 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6399 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6400 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6401 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6402 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6403 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6404 TmpInst.addOperand(Inst.getOperand(4));
6409 case ARM::VLD3DUPdWB_register_Asm_8:
6410 case ARM::VLD3DUPdWB_register_Asm_16:
6411 case ARM::VLD3DUPdWB_register_Asm_32:
6412 case ARM::VLD3DUPqWB_register_Asm_8:
6413 case ARM::VLD3DUPqWB_register_Asm_16:
6414 case ARM::VLD3DUPqWB_register_Asm_32: {
6417 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6418 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6419 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6421 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6423 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6424 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6425 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6426 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6427 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6428 TmpInst.addOperand(Inst.getOperand(5));
6433 // VLD3 multiple 3-element structure instructions.
6434 case ARM::VLD3dAsm_8:
6435 case ARM::VLD3dAsm_16:
6436 case ARM::VLD3dAsm_32:
6437 case ARM::VLD3qAsm_8:
6438 case ARM::VLD3qAsm_16:
6439 case ARM::VLD3qAsm_32: {
6442 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6443 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6448 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6449 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6450 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6451 TmpInst.addOperand(Inst.getOperand(4));
6456 case ARM::VLD3dWB_fixed_Asm_8:
6457 case ARM::VLD3dWB_fixed_Asm_16:
6458 case ARM::VLD3dWB_fixed_Asm_32:
6459 case ARM::VLD3qWB_fixed_Asm_8:
6460 case ARM::VLD3qWB_fixed_Asm_16:
6461 case ARM::VLD3qWB_fixed_Asm_32: {
6464 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6465 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6466 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6471 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6472 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6473 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6474 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6475 TmpInst.addOperand(Inst.getOperand(4));
6480 case ARM::VLD3dWB_register_Asm_8:
6481 case ARM::VLD3dWB_register_Asm_16:
6482 case ARM::VLD3dWB_register_Asm_32:
6483 case ARM::VLD3qWB_register_Asm_8:
6484 case ARM::VLD3qWB_register_Asm_16:
6485 case ARM::VLD3qWB_register_Asm_32: {
6488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6489 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6490 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6494 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6495 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6496 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6497 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6498 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6499 TmpInst.addOperand(Inst.getOperand(5));
6504 // VLD4DUP single 3-element structure to all lanes instructions.
6505 case ARM::VLD4DUPdAsm_8:
6506 case ARM::VLD4DUPdAsm_16:
6507 case ARM::VLD4DUPdAsm_32:
6508 case ARM::VLD4DUPqAsm_8:
6509 case ARM::VLD4DUPqAsm_16:
6510 case ARM::VLD4DUPqAsm_32: {
6513 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6514 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6515 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6522 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6523 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6524 TmpInst.addOperand(Inst.getOperand(4));
6529 case ARM::VLD4DUPdWB_fixed_Asm_8:
6530 case ARM::VLD4DUPdWB_fixed_Asm_16:
6531 case ARM::VLD4DUPdWB_fixed_Asm_32:
6532 case ARM::VLD4DUPqWB_fixed_Asm_8:
6533 case ARM::VLD4DUPqWB_fixed_Asm_16:
6534 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6537 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6538 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6546 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6547 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6548 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6549 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6550 TmpInst.addOperand(Inst.getOperand(4));
6555 case ARM::VLD4DUPdWB_register_Asm_8:
6556 case ARM::VLD4DUPdWB_register_Asm_16:
6557 case ARM::VLD4DUPdWB_register_Asm_32:
6558 case ARM::VLD4DUPqWB_register_Asm_8:
6559 case ARM::VLD4DUPqWB_register_Asm_16:
6560 case ARM::VLD4DUPqWB_register_Asm_32: {
6563 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6564 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6565 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6567 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6571 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6572 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6573 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6574 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6575 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6576 TmpInst.addOperand(Inst.getOperand(5));
6581 // VLD4 multiple 4-element structure instructions.
6582 case ARM::VLD4dAsm_8:
6583 case ARM::VLD4dAsm_16:
6584 case ARM::VLD4dAsm_32:
6585 case ARM::VLD4qAsm_8:
6586 case ARM::VLD4qAsm_16:
6587 case ARM::VLD4qAsm_32: {
6590 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6591 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6592 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6594 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6596 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6598 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6599 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6600 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6601 TmpInst.addOperand(Inst.getOperand(4));
6606 case ARM::VLD4dWB_fixed_Asm_8:
6607 case ARM::VLD4dWB_fixed_Asm_16:
6608 case ARM::VLD4dWB_fixed_Asm_32:
6609 case ARM::VLD4qWB_fixed_Asm_8:
6610 case ARM::VLD4qWB_fixed_Asm_16:
6611 case ARM::VLD4qWB_fixed_Asm_32: {
6614 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6615 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6616 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6623 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6624 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6625 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6626 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6627 TmpInst.addOperand(Inst.getOperand(4));
6632 case ARM::VLD4dWB_register_Asm_8:
6633 case ARM::VLD4dWB_register_Asm_16:
6634 case ARM::VLD4dWB_register_Asm_32:
6635 case ARM::VLD4qWB_register_Asm_8:
6636 case ARM::VLD4qWB_register_Asm_16:
6637 case ARM::VLD4qWB_register_Asm_32: {
6640 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6641 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6642 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6648 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6649 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6650 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6651 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6652 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6653 TmpInst.addOperand(Inst.getOperand(5));
6658 // VST3 multiple 3-element structure instructions.
6659 case ARM::VST3dAsm_8:
6660 case ARM::VST3dAsm_16:
6661 case ARM::VST3dAsm_32:
6662 case ARM::VST3qAsm_8:
6663 case ARM::VST3qAsm_16:
6664 case ARM::VST3qAsm_32: {
6667 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6668 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6669 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6670 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6671 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6675 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6676 TmpInst.addOperand(Inst.getOperand(4));
6681 case ARM::VST3dWB_fixed_Asm_8:
6682 case ARM::VST3dWB_fixed_Asm_16:
6683 case ARM::VST3dWB_fixed_Asm_32:
6684 case ARM::VST3qWB_fixed_Asm_8:
6685 case ARM::VST3qWB_fixed_Asm_16:
6686 case ARM::VST3qWB_fixed_Asm_32: {
6689 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6690 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6691 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6692 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6693 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6694 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6695 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6697 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6699 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6700 TmpInst.addOperand(Inst.getOperand(4));
6705 case ARM::VST3dWB_register_Asm_8:
6706 case ARM::VST3dWB_register_Asm_16:
6707 case ARM::VST3dWB_register_Asm_32:
6708 case ARM::VST3qWB_register_Asm_8:
6709 case ARM::VST3qWB_register_Asm_16:
6710 case ARM::VST3qWB_register_Asm_32: {
6713 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6714 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6715 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6716 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6717 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6718 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6719 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6723 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6724 TmpInst.addOperand(Inst.getOperand(5));
6729 // VST4 multiple 3-element structure instructions.
6730 case ARM::VST4dAsm_8:
6731 case ARM::VST4dAsm_16:
6732 case ARM::VST4dAsm_32:
6733 case ARM::VST4qAsm_8:
6734 case ARM::VST4qAsm_16:
6735 case ARM::VST4qAsm_32: {
6738 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6739 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6740 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6741 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6742 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6744 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6746 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6748 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6749 TmpInst.addOperand(Inst.getOperand(4));
6754 case ARM::VST4dWB_fixed_Asm_8:
6755 case ARM::VST4dWB_fixed_Asm_16:
6756 case ARM::VST4dWB_fixed_Asm_32:
6757 case ARM::VST4qWB_fixed_Asm_8:
6758 case ARM::VST4qWB_fixed_Asm_16:
6759 case ARM::VST4qWB_fixed_Asm_32: {
6762 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6763 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6764 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6765 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6766 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6767 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6768 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6770 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6774 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6775 TmpInst.addOperand(Inst.getOperand(4));
6780 case ARM::VST4dWB_register_Asm_8:
6781 case ARM::VST4dWB_register_Asm_16:
6782 case ARM::VST4dWB_register_Asm_32:
6783 case ARM::VST4qWB_register_Asm_8:
6784 case ARM::VST4qWB_register_Asm_16:
6785 case ARM::VST4qWB_register_Asm_32: {
6788 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6789 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6790 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6791 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6792 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6793 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6794 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6796 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6800 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6801 TmpInst.addOperand(Inst.getOperand(5));
6806 // Handle encoding choice for the shift-immediate instructions.
6809 case ARM::t2ASRri: {
6810 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6811 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6812 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6813 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6814 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6816 switch (Inst.getOpcode()) {
6817 default: llvm_unreachable("unexpected opcode");
6818 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6819 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6820 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6822 // The Thumb1 operands aren't in the same order. Awesome, eh?
6824 TmpInst.setOpcode(NewOpc);
6825 TmpInst.addOperand(Inst.getOperand(0));
6826 TmpInst.addOperand(Inst.getOperand(5));
6827 TmpInst.addOperand(Inst.getOperand(1));
6828 TmpInst.addOperand(Inst.getOperand(2));
6829 TmpInst.addOperand(Inst.getOperand(3));
6830 TmpInst.addOperand(Inst.getOperand(4));
6837 // Handle the Thumb2 mode MOV complex aliases.
6839 case ARM::t2MOVSsr: {
6840 // Which instruction to expand to depends on the CCOut operand and
6841 // whether we're in an IT block if the register operands are low
6843 bool isNarrow = false;
6844 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6845 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6846 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6847 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6848 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6852 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6853 default: llvm_unreachable("unexpected opcode!");
6854 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6855 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6856 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6857 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6859 TmpInst.setOpcode(newOpc);
6860 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6862 TmpInst.addOperand(MCOperand::CreateReg(
6863 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6864 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6865 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6866 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6867 TmpInst.addOperand(Inst.getOperand(5));
6869 TmpInst.addOperand(MCOperand::CreateReg(
6870 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6875 case ARM::t2MOVSsi: {
6876 // Which instruction to expand to depends on the CCOut operand and
6877 // whether we're in an IT block if the register operands are low
6879 bool isNarrow = false;
6880 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6881 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6882 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6886 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6887 default: llvm_unreachable("unexpected opcode!");
6888 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6889 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6890 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6891 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6892 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6894 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6895 if (Amount == 32) Amount = 0;
6896 TmpInst.setOpcode(newOpc);
6897 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6899 TmpInst.addOperand(MCOperand::CreateReg(
6900 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6901 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6902 if (newOpc != ARM::t2RRX)
6903 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6904 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6905 TmpInst.addOperand(Inst.getOperand(4));
6907 TmpInst.addOperand(MCOperand::CreateReg(
6908 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6912 // Handle the ARM mode MOV complex aliases.
6917 ARM_AM::ShiftOpc ShiftTy;
6918 switch(Inst.getOpcode()) {
6919 default: llvm_unreachable("unexpected opcode!");
6920 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6921 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6922 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6923 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6925 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6927 TmpInst.setOpcode(ARM::MOVsr);
6928 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6929 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6930 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6931 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6932 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6933 TmpInst.addOperand(Inst.getOperand(4));
6934 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6942 ARM_AM::ShiftOpc ShiftTy;
6943 switch(Inst.getOpcode()) {
6944 default: llvm_unreachable("unexpected opcode!");
6945 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6946 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6947 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6948 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6950 // A shift by zero is a plain MOVr, not a MOVsi.
6951 unsigned Amt = Inst.getOperand(2).getImm();
6952 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6953 // A shift by 32 should be encoded as 0 when permitted
6954 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6956 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6958 TmpInst.setOpcode(Opc);
6959 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6960 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6961 if (Opc == ARM::MOVsi)
6962 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6963 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6964 TmpInst.addOperand(Inst.getOperand(4));
6965 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6970 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6972 TmpInst.setOpcode(ARM::MOVsi);
6973 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6974 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6975 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6976 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6977 TmpInst.addOperand(Inst.getOperand(3));
6978 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6982 case ARM::t2LDMIA_UPD: {
6983 // If this is a load of a single register, then we should use
6984 // a post-indexed LDR instruction instead, per the ARM ARM.
6985 if (Inst.getNumOperands() != 5)
6988 TmpInst.setOpcode(ARM::t2LDR_POST);
6989 TmpInst.addOperand(Inst.getOperand(4)); // Rt
6990 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6991 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6992 TmpInst.addOperand(MCOperand::CreateImm(4));
6993 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6994 TmpInst.addOperand(Inst.getOperand(3));
6998 case ARM::t2STMDB_UPD: {
6999 // If this is a store of a single register, then we should use
7000 // a pre-indexed STR instruction instead, per the ARM ARM.
7001 if (Inst.getNumOperands() != 5)
7004 TmpInst.setOpcode(ARM::t2STR_PRE);
7005 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7006 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7007 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7008 TmpInst.addOperand(MCOperand::CreateImm(-4));
7009 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7010 TmpInst.addOperand(Inst.getOperand(3));
7014 case ARM::LDMIA_UPD:
7015 // If this is a load of a single register via a 'pop', then we should use
7016 // a post-indexed LDR instruction instead, per the ARM ARM.
7017 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7018 Inst.getNumOperands() == 5) {
7020 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7021 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7022 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7023 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7024 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7025 TmpInst.addOperand(MCOperand::CreateImm(4));
7026 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7027 TmpInst.addOperand(Inst.getOperand(3));
7032 case ARM::STMDB_UPD:
7033 // If this is a store of a single register via a 'push', then we should use
7034 // a pre-indexed STR instruction instead, per the ARM ARM.
7035 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7036 Inst.getNumOperands() == 5) {
7038 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7039 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7040 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7041 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7042 TmpInst.addOperand(MCOperand::CreateImm(-4));
7043 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7044 TmpInst.addOperand(Inst.getOperand(3));
7048 case ARM::t2ADDri12:
7049 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7050 // mnemonic was used (not "addw"), encoding T3 is preferred.
7051 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7052 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7054 Inst.setOpcode(ARM::t2ADDri);
7055 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7057 case ARM::t2SUBri12:
7058 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7059 // mnemonic was used (not "subw"), encoding T3 is preferred.
7060 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7061 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7063 Inst.setOpcode(ARM::t2SUBri);
7064 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7067 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7068 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7069 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7070 // to encoding T1 if <Rd> is omitted."
7071 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7072 Inst.setOpcode(ARM::tADDi3);
7077 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7078 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7079 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7080 // to encoding T1 if <Rd> is omitted."
7081 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7082 Inst.setOpcode(ARM::tSUBi3);
7087 case ARM::t2SUBri: {
7088 // If the destination and first source operand are the same, and
7089 // the flags are compatible with the current IT status, use encoding T2
7090 // instead of T3. For compatibility with the system 'as'. Make sure the
7091 // wide encoding wasn't explicit.
7092 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7093 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7094 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7095 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7096 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7097 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7098 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7101 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7102 ARM::tADDi8 : ARM::tSUBi8);
7103 TmpInst.addOperand(Inst.getOperand(0));
7104 TmpInst.addOperand(Inst.getOperand(5));
7105 TmpInst.addOperand(Inst.getOperand(0));
7106 TmpInst.addOperand(Inst.getOperand(2));
7107 TmpInst.addOperand(Inst.getOperand(3));
7108 TmpInst.addOperand(Inst.getOperand(4));
7112 case ARM::t2ADDrr: {
7113 // If the destination and first source operand are the same, and
7114 // there's no setting of the flags, use encoding T2 instead of T3.
7115 // Note that this is only for ADD, not SUB. This mirrors the system
7116 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7117 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7118 Inst.getOperand(5).getReg() != 0 ||
7119 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7120 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7123 TmpInst.setOpcode(ARM::tADDhirr);
7124 TmpInst.addOperand(Inst.getOperand(0));
7125 TmpInst.addOperand(Inst.getOperand(0));
7126 TmpInst.addOperand(Inst.getOperand(2));
7127 TmpInst.addOperand(Inst.getOperand(3));
7128 TmpInst.addOperand(Inst.getOperand(4));
7132 case ARM::tADDrSP: {
7133 // If the non-SP source operand and the destination operand are not the
7134 // same, we need to use the 32-bit encoding if it's available.
7135 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7136 Inst.setOpcode(ARM::t2ADDrr);
7137 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7143 // A Thumb conditional branch outside of an IT block is a tBcc.
7144 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7145 Inst.setOpcode(ARM::tBcc);
7150 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7151 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7152 Inst.setOpcode(ARM::t2Bcc);
7157 // If the conditional is AL or we're in an IT block, we really want t2B.
7158 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7159 Inst.setOpcode(ARM::t2B);
7164 // If the conditional is AL, we really want tB.
7165 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7166 Inst.setOpcode(ARM::tB);
7171 // If the register list contains any high registers, or if the writeback
7172 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7173 // instead if we're in Thumb2. Otherwise, this should have generated
7174 // an error in validateInstruction().
7175 unsigned Rn = Inst.getOperand(0).getReg();
7176 bool hasWritebackToken =
7177 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7178 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7179 bool listContainsBase;
7180 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7181 (!listContainsBase && !hasWritebackToken) ||
7182 (listContainsBase && hasWritebackToken)) {
7183 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7184 assert (isThumbTwo());
7185 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7186 // If we're switching to the updating version, we need to insert
7187 // the writeback tied operand.
7188 if (hasWritebackToken)
7189 Inst.insert(Inst.begin(),
7190 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7195 case ARM::tSTMIA_UPD: {
7196 // If the register list contains any high registers, we need to use
7197 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7198 // should have generated an error in validateInstruction().
7199 unsigned Rn = Inst.getOperand(0).getReg();
7200 bool listContainsBase;
7201 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7202 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7203 assert (isThumbTwo());
7204 Inst.setOpcode(ARM::t2STMIA_UPD);
7210 bool listContainsBase;
7211 // If the register list contains any high registers, we need to use
7212 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7213 // should have generated an error in validateInstruction().
7214 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7216 assert (isThumbTwo());
7217 Inst.setOpcode(ARM::t2LDMIA_UPD);
7218 // Add the base register and writeback operands.
7219 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7220 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7224 bool listContainsBase;
7225 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7227 assert (isThumbTwo());
7228 Inst.setOpcode(ARM::t2STMDB_UPD);
7229 // Add the base register and writeback operands.
7230 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7231 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7235 // If we can use the 16-bit encoding and the user didn't explicitly
7236 // request the 32-bit variant, transform it here.
7237 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7238 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7239 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7240 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7241 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7242 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7243 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7244 // The operands aren't in the same order for tMOVi8...
7246 TmpInst.setOpcode(ARM::tMOVi8);
7247 TmpInst.addOperand(Inst.getOperand(0));
7248 TmpInst.addOperand(Inst.getOperand(4));
7249 TmpInst.addOperand(Inst.getOperand(1));
7250 TmpInst.addOperand(Inst.getOperand(2));
7251 TmpInst.addOperand(Inst.getOperand(3));
7258 // If we can use the 16-bit encoding and the user didn't explicitly
7259 // request the 32-bit variant, transform it here.
7260 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7261 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7262 Inst.getOperand(2).getImm() == ARMCC::AL &&
7263 Inst.getOperand(4).getReg() == ARM::CPSR &&
7264 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7265 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7266 // The operands aren't the same for tMOV[S]r... (no cc_out)
7268 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7269 TmpInst.addOperand(Inst.getOperand(0));
7270 TmpInst.addOperand(Inst.getOperand(1));
7271 TmpInst.addOperand(Inst.getOperand(2));
7272 TmpInst.addOperand(Inst.getOperand(3));
7282 // If we can use the 16-bit encoding and the user didn't explicitly
7283 // request the 32-bit variant, transform it here.
7284 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7285 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7286 Inst.getOperand(2).getImm() == 0 &&
7287 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7288 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7290 switch (Inst.getOpcode()) {
7291 default: llvm_unreachable("Illegal opcode!");
7292 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7293 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7294 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7295 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7297 // The operands aren't the same for thumb1 (no rotate operand).
7299 TmpInst.setOpcode(NewOpc);
7300 TmpInst.addOperand(Inst.getOperand(0));
7301 TmpInst.addOperand(Inst.getOperand(1));
7302 TmpInst.addOperand(Inst.getOperand(3));
7303 TmpInst.addOperand(Inst.getOperand(4));
7310 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7311 // rrx shifts and asr/lsr of #32 is encoded as 0
7312 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7314 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7315 // Shifting by zero is accepted as a vanilla 'MOVr'
7317 TmpInst.setOpcode(ARM::MOVr);
7318 TmpInst.addOperand(Inst.getOperand(0));
7319 TmpInst.addOperand(Inst.getOperand(1));
7320 TmpInst.addOperand(Inst.getOperand(3));
7321 TmpInst.addOperand(Inst.getOperand(4));
7322 TmpInst.addOperand(Inst.getOperand(5));
7335 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7336 if (SOpc == ARM_AM::rrx) return false;
7337 switch (Inst.getOpcode()) {
7338 default: llvm_unreachable("unexpected opcode!");
7339 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7340 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7341 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7342 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7343 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7344 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7346 // If the shift is by zero, use the non-shifted instruction definition.
7347 // The exception is for right shifts, where 0 == 32
7348 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7349 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7351 TmpInst.setOpcode(newOpc);
7352 TmpInst.addOperand(Inst.getOperand(0));
7353 TmpInst.addOperand(Inst.getOperand(1));
7354 TmpInst.addOperand(Inst.getOperand(2));
7355 TmpInst.addOperand(Inst.getOperand(4));
7356 TmpInst.addOperand(Inst.getOperand(5));
7357 TmpInst.addOperand(Inst.getOperand(6));
7365 // The mask bits for all but the first condition are represented as
7366 // the low bit of the condition code value implies 't'. We currently
7367 // always have 1 implies 't', so XOR toggle the bits if the low bit
7368 // of the condition code is zero.
7369 MCOperand &MO = Inst.getOperand(1);
7370 unsigned Mask = MO.getImm();
7371 unsigned OrigMask = Mask;
7372 unsigned TZ = CountTrailingZeros_32(Mask);
7373 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7374 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7375 for (unsigned i = 3; i != TZ; --i)
7380 // Set up the IT block state according to the IT instruction we just
7382 assert(!inITBlock() && "nested IT blocks?!");
7383 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7384 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7385 ITState.CurPosition = 0;
7386 ITState.FirstCond = true;
7396 // Assemblers should use the narrow encodings of these instructions when permissible.
7397 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7398 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7399 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7400 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7401 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7402 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7403 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7405 switch (Inst.getOpcode()) {
7406 default: llvm_unreachable("unexpected opcode");
7407 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7408 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7409 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7410 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7411 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7412 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7415 TmpInst.setOpcode(NewOpc);
7416 TmpInst.addOperand(Inst.getOperand(0));
7417 TmpInst.addOperand(Inst.getOperand(5));
7418 TmpInst.addOperand(Inst.getOperand(1));
7419 TmpInst.addOperand(Inst.getOperand(2));
7420 TmpInst.addOperand(Inst.getOperand(3));
7421 TmpInst.addOperand(Inst.getOperand(4));
7432 // Assemblers should use the narrow encodings of these instructions when permissible.
7433 // These instructions are special in that they are commutable, so shorter encodings
7434 // are available more often.
7435 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7436 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7437 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7438 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7439 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7440 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7441 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7442 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7444 switch (Inst.getOpcode()) {
7445 default: llvm_unreachable("unexpected opcode");
7446 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7447 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7448 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7449 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7452 TmpInst.setOpcode(NewOpc);
7453 TmpInst.addOperand(Inst.getOperand(0));
7454 TmpInst.addOperand(Inst.getOperand(5));
7455 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7456 TmpInst.addOperand(Inst.getOperand(1));
7457 TmpInst.addOperand(Inst.getOperand(2));
7459 TmpInst.addOperand(Inst.getOperand(2));
7460 TmpInst.addOperand(Inst.getOperand(1));
7462 TmpInst.addOperand(Inst.getOperand(3));
7463 TmpInst.addOperand(Inst.getOperand(4));
7473 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7474 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7475 // suffix depending on whether they're in an IT block or not.
7476 unsigned Opc = Inst.getOpcode();
7477 const MCInstrDesc &MCID = getInstDesc(Opc);
7478 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7479 assert(MCID.hasOptionalDef() &&
7480 "optionally flag setting instruction missing optional def operand");
7481 assert(MCID.NumOperands == Inst.getNumOperands() &&
7482 "operand count mismatch!");
7483 // Find the optional-def operand (cc_out).
7486 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7489 // If we're parsing Thumb1, reject it completely.
7490 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7491 return Match_MnemonicFail;
7492 // If we're parsing Thumb2, which form is legal depends on whether we're
7494 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7496 return Match_RequiresITBlock;
7497 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7499 return Match_RequiresNotITBlock;
7501 // Some high-register supporting Thumb1 encodings only allow both registers
7502 // to be from r0-r7 when in Thumb2.
7503 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7504 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7505 isARMLowRegister(Inst.getOperand(2).getReg()))
7506 return Match_RequiresThumb2;
7507 // Others only require ARMv6 or later.
7508 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7509 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7510 isARMLowRegister(Inst.getOperand(1).getReg()))
7511 return Match_RequiresV6;
7512 return Match_Success;
7515 static const char *getSubtargetFeatureName(unsigned Val);
7517 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7518 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7519 MCStreamer &Out, unsigned &ErrorInfo,
7520 bool MatchingInlineAsm) {
7522 unsigned MatchResult;
7524 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7526 switch (MatchResult) {
7529 // Context sensitive operand constraints aren't handled by the matcher,
7530 // so check them here.
7531 if (validateInstruction(Inst, Operands)) {
7532 // Still progress the IT block, otherwise one wrong condition causes
7533 // nasty cascading errors.
7534 forwardITPosition();
7538 // Some instructions need post-processing to, for example, tweak which
7539 // encoding is selected. Loop on it while changes happen so the
7540 // individual transformations can chain off each other. E.g.,
7541 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7542 while (processInstruction(Inst, Operands))
7545 // Only move forward at the very end so that everything in validate
7546 // and process gets a consistent answer about whether we're in an IT
7548 forwardITPosition();
7550 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7551 // doesn't actually encode.
7552 if (Inst.getOpcode() == ARM::ITasm)
7556 Out.EmitInstruction(Inst);
7558 case Match_MissingFeature: {
7559 assert(ErrorInfo && "Unknown missing feature!");
7560 // Special case the error message for the very common case where only
7561 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7562 std::string Msg = "instruction requires:";
7564 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7565 if (ErrorInfo & Mask) {
7567 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7571 return Error(IDLoc, Msg);
7573 case Match_InvalidOperand: {
7574 SMLoc ErrorLoc = IDLoc;
7575 if (ErrorInfo != ~0U) {
7576 if (ErrorInfo >= Operands.size())
7577 return Error(IDLoc, "too few operands for instruction");
7579 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7580 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7583 return Error(ErrorLoc, "invalid operand for instruction");
7585 case Match_MnemonicFail:
7586 return Error(IDLoc, "invalid instruction",
7587 ((ARMOperand*)Operands[0])->getLocRange());
7588 case Match_RequiresNotITBlock:
7589 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7590 case Match_RequiresITBlock:
7591 return Error(IDLoc, "instruction only valid inside IT block");
7592 case Match_RequiresV6:
7593 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7594 case Match_RequiresThumb2:
7595 return Error(IDLoc, "instruction variant requires Thumb2");
7596 case Match_ImmRange0_15: {
7597 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7598 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7599 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7603 llvm_unreachable("Implement any new match types added!");
7606 /// parseDirective parses the arm specific directives
7607 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7608 StringRef IDVal = DirectiveID.getIdentifier();
7609 if (IDVal == ".word")
7610 return parseDirectiveWord(4, DirectiveID.getLoc());
7611 else if (IDVal == ".thumb")
7612 return parseDirectiveThumb(DirectiveID.getLoc());
7613 else if (IDVal == ".arm")
7614 return parseDirectiveARM(DirectiveID.getLoc());
7615 else if (IDVal == ".thumb_func")
7616 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7617 else if (IDVal == ".code")
7618 return parseDirectiveCode(DirectiveID.getLoc());
7619 else if (IDVal == ".syntax")
7620 return parseDirectiveSyntax(DirectiveID.getLoc());
7621 else if (IDVal == ".unreq")
7622 return parseDirectiveUnreq(DirectiveID.getLoc());
7623 else if (IDVal == ".arch")
7624 return parseDirectiveArch(DirectiveID.getLoc());
7625 else if (IDVal == ".eabi_attribute")
7626 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7630 /// parseDirectiveWord
7631 /// ::= .word [ expression (, expression)* ]
7632 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7633 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7635 const MCExpr *Value;
7636 if (getParser().ParseExpression(Value))
7639 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7641 if (getLexer().is(AsmToken::EndOfStatement))
7644 // FIXME: Improve diagnostic.
7645 if (getLexer().isNot(AsmToken::Comma))
7646 return Error(L, "unexpected token in directive");
7655 /// parseDirectiveThumb
7657 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7658 if (getLexer().isNot(AsmToken::EndOfStatement))
7659 return Error(L, "unexpected token in directive");
7664 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7668 /// parseDirectiveARM
7670 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7671 if (getLexer().isNot(AsmToken::EndOfStatement))
7672 return Error(L, "unexpected token in directive");
7677 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7681 /// parseDirectiveThumbFunc
7682 /// ::= .thumbfunc symbol_name
7683 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7684 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7685 bool isMachO = MAI.hasSubsectionsViaSymbols();
7687 bool needFuncName = true;
7689 // Darwin asm has (optionally) function name after .thumb_func direction
7692 const AsmToken &Tok = Parser.getTok();
7693 if (Tok.isNot(AsmToken::EndOfStatement)) {
7694 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7695 return Error(L, "unexpected token in .thumb_func directive");
7696 Name = Tok.getIdentifier();
7697 Parser.Lex(); // Consume the identifier token.
7698 needFuncName = false;
7702 if (getLexer().isNot(AsmToken::EndOfStatement))
7703 return Error(L, "unexpected token in directive");
7705 // Eat the end of statement and any blank lines that follow.
7706 while (getLexer().is(AsmToken::EndOfStatement))
7709 // FIXME: assuming function name will be the line following .thumb_func
7710 // We really should be checking the next symbol definition even if there's
7711 // stuff in between.
7713 Name = Parser.getTok().getIdentifier();
7716 // Mark symbol as a thumb symbol.
7717 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7718 getParser().getStreamer().EmitThumbFunc(Func);
7722 /// parseDirectiveSyntax
7723 /// ::= .syntax unified | divided
7724 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7725 const AsmToken &Tok = Parser.getTok();
7726 if (Tok.isNot(AsmToken::Identifier))
7727 return Error(L, "unexpected token in .syntax directive");
7728 StringRef Mode = Tok.getString();
7729 if (Mode == "unified" || Mode == "UNIFIED")
7731 else if (Mode == "divided" || Mode == "DIVIDED")
7732 return Error(L, "'.syntax divided' arm asssembly not supported");
7734 return Error(L, "unrecognized syntax mode in .syntax directive");
7736 if (getLexer().isNot(AsmToken::EndOfStatement))
7737 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7740 // TODO tell the MC streamer the mode
7741 // getParser().getStreamer().Emit???();
7745 /// parseDirectiveCode
7746 /// ::= .code 16 | 32
7747 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7748 const AsmToken &Tok = Parser.getTok();
7749 if (Tok.isNot(AsmToken::Integer))
7750 return Error(L, "unexpected token in .code directive");
7751 int64_t Val = Parser.getTok().getIntVal();
7757 return Error(L, "invalid operand to .code directive");
7759 if (getLexer().isNot(AsmToken::EndOfStatement))
7760 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7766 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7770 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7776 /// parseDirectiveReq
7777 /// ::= name .req registername
7778 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7779 Parser.Lex(); // Eat the '.req' token.
7781 SMLoc SRegLoc, ERegLoc;
7782 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7783 Parser.EatToEndOfStatement();
7784 return Error(SRegLoc, "register name expected");
7787 // Shouldn't be anything else.
7788 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7789 Parser.EatToEndOfStatement();
7790 return Error(Parser.getTok().getLoc(),
7791 "unexpected input in .req directive.");
7794 Parser.Lex(); // Consume the EndOfStatement
7796 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7797 return Error(SRegLoc, "redefinition of '" + Name +
7798 "' does not match original.");
7803 /// parseDirectiveUneq
7804 /// ::= .unreq registername
7805 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7806 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7807 Parser.EatToEndOfStatement();
7808 return Error(L, "unexpected input in .unreq directive.");
7810 RegisterReqs.erase(Parser.getTok().getIdentifier());
7811 Parser.Lex(); // Eat the identifier.
7815 /// parseDirectiveArch
7817 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7821 /// parseDirectiveEabiAttr
7822 /// ::= .eabi_attribute int, int
7823 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7827 extern "C" void LLVMInitializeARMAsmLexer();
7829 /// Force static initialization.
7830 extern "C" void LLVMInitializeARMAsmParser() {
7831 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7832 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7833 LLVMInitializeARMAsmLexer();
7836 #define GET_REGISTER_MATCHER
7837 #define GET_SUBTARGET_FEATURE_NAME
7838 #define GET_MATCHER_IMPLEMENTATION
7839 #include "ARMGenAsmMatcher.inc"