1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 const MCExpr *applyPrefixToExpr(const MCExpr *E,
91 MCSymbolRefExpr::VariantKind Variant);
94 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
95 unsigned &ShiftAmount);
96 bool parseDirectiveWord(unsigned Size, SMLoc L);
97 bool parseDirectiveThumb(SMLoc L);
98 bool parseDirectiveThumbFunc(SMLoc L);
99 bool parseDirectiveCode(SMLoc L);
100 bool parseDirectiveSyntax(SMLoc L);
102 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
103 bool &CarrySetting, unsigned &ProcessorIMod,
105 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
106 bool &CanAcceptPredicationCode);
108 bool isThumb() const {
109 // FIXME: Can tablegen auto-generate this?
110 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
112 bool isThumbOne() const {
113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
115 bool isThumbTwo() const {
116 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
118 bool hasV6Ops() const {
119 return STI.getFeatureBits() & ARM::HasV6Ops;
122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123 setAvailableFeatures(FB);
126 /// @name Auto-generated Match Functions
129 #define GET_ASSEMBLER_HEADER
130 #include "ARMGenAsmMatcher.inc"
134 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
135 OperandMatchResultTy parseCoprocNumOperand(
136 SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseCoprocRegOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseMemBarrierOptOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parseProcIFlagsOperand(
142 SmallVectorImpl<MCParsedAsmOperand*>&);
143 OperandMatchResultTy parseMSRMaskOperand(
144 SmallVectorImpl<MCParsedAsmOperand*>&);
145 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
146 StringRef Op, int Low, int High);
147 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
148 return parsePKHImm(O, "lsl", 0, 31);
150 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
151 return parsePKHImm(O, "asr", 1, 32);
153 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
154 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
156 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
158 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
160 // Asm Match Converter Methods
161 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
162 const SmallVectorImpl<MCParsedAsmOperand*> &);
163 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
164 const SmallVectorImpl<MCParsedAsmOperand*> &);
165 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
166 const SmallVectorImpl<MCParsedAsmOperand*> &);
167 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
188 bool validateInstruction(MCInst &Inst,
189 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
190 void processInstruction(MCInst &Inst,
191 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
192 bool shouldOmitCCOutOperand(StringRef Mnemonic,
193 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
196 enum ARMMatchResultTy {
197 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
198 Match_RequiresNotITBlock,
203 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
204 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
205 MCAsmParserExtension::Initialize(_Parser);
207 // Initialize the set of available features.
208 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
210 // Not in an ITBlock to start with.
211 ITState.CurPosition = ~0U;
214 // Implementation of the MCTargetAsmParser interface:
215 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
216 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
217 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
218 bool ParseDirective(AsmToken DirectiveID);
220 unsigned checkTargetMatchPredicate(MCInst &Inst);
222 bool MatchAndEmitInstruction(SMLoc IDLoc,
223 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
226 } // end anonymous namespace
230 /// ARMOperand - Instances of this class represent a parsed ARM machine
232 class ARMOperand : public MCParsedAsmOperand {
257 SMLoc StartLoc, EndLoc;
258 SmallVector<unsigned, 8> Registers;
262 ARMCC::CondCodes Val;
278 ARM_PROC::IFlags Val;
298 /// Combined record for all forms of ARM address expressions.
301 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
303 const MCConstantExpr *OffsetImm; // Offset immediate value
304 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
305 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
306 unsigned ShiftImm; // shift for OffsetReg.
307 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
313 ARM_AM::ShiftOpc ShiftTy;
322 ARM_AM::ShiftOpc ShiftTy;
328 ARM_AM::ShiftOpc ShiftTy;
341 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
343 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
345 StartLoc = o.StartLoc;
362 case DPRRegisterList:
363 case SPRRegisterList:
364 Registers = o.Registers;
379 case PostIndexRegister:
380 PostIdxReg = o.PostIdxReg;
388 case ShifterImmediate:
389 ShifterImm = o.ShifterImm;
391 case ShiftedRegister:
392 RegShiftedReg = o.RegShiftedReg;
394 case ShiftedImmediate:
395 RegShiftedImm = o.RegShiftedImm;
397 case RotateImmediate:
400 case BitfieldDescriptor:
401 Bitfield = o.Bitfield;
406 /// getStartLoc - Get the location of the first token of this operand.
407 SMLoc getStartLoc() const { return StartLoc; }
408 /// getEndLoc - Get the location of the last token of this operand.
409 SMLoc getEndLoc() const { return EndLoc; }
411 ARMCC::CondCodes getCondCode() const {
412 assert(Kind == CondCode && "Invalid access!");
416 unsigned getCoproc() const {
417 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
421 StringRef getToken() const {
422 assert(Kind == Token && "Invalid access!");
423 return StringRef(Tok.Data, Tok.Length);
426 unsigned getReg() const {
427 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
431 const SmallVectorImpl<unsigned> &getRegList() const {
432 assert((Kind == RegisterList || Kind == DPRRegisterList ||
433 Kind == SPRRegisterList) && "Invalid access!");
437 const MCExpr *getImm() const {
438 assert(Kind == Immediate && "Invalid access!");
442 ARM_MB::MemBOpt getMemBarrierOpt() const {
443 assert(Kind == MemBarrierOpt && "Invalid access!");
447 ARM_PROC::IFlags getProcIFlags() const {
448 assert(Kind == ProcIFlags && "Invalid access!");
452 unsigned getMSRMask() const {
453 assert(Kind == MSRMask && "Invalid access!");
457 bool isCoprocNum() const { return Kind == CoprocNum; }
458 bool isCoprocReg() const { return Kind == CoprocReg; }
459 bool isCondCode() const { return Kind == CondCode; }
460 bool isCCOut() const { return Kind == CCOut; }
461 bool isITMask() const { return Kind == ITCondMask; }
462 bool isITCondCode() const { return Kind == CondCode; }
463 bool isImm() const { return Kind == Immediate; }
464 bool isImm0_1020s4() const {
465 if (Kind != Immediate)
467 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
468 if (!CE) return false;
469 int64_t Value = CE->getValue();
470 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
472 bool isImm0_508s4() const {
473 if (Kind != Immediate)
475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
476 if (!CE) return false;
477 int64_t Value = CE->getValue();
478 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
480 bool isImm0_255() const {
481 if (Kind != Immediate)
483 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
484 if (!CE) return false;
485 int64_t Value = CE->getValue();
486 return Value >= 0 && Value < 256;
488 bool isImm0_7() const {
489 if (Kind != Immediate)
491 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492 if (!CE) return false;
493 int64_t Value = CE->getValue();
494 return Value >= 0 && Value < 8;
496 bool isImm0_15() const {
497 if (Kind != Immediate)
499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500 if (!CE) return false;
501 int64_t Value = CE->getValue();
502 return Value >= 0 && Value < 16;
504 bool isImm0_31() const {
505 if (Kind != Immediate)
507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508 if (!CE) return false;
509 int64_t Value = CE->getValue();
510 return Value >= 0 && Value < 32;
512 bool isImm1_16() const {
513 if (Kind != Immediate)
515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516 if (!CE) return false;
517 int64_t Value = CE->getValue();
518 return Value > 0 && Value < 17;
520 bool isImm1_32() const {
521 if (Kind != Immediate)
523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524 if (!CE) return false;
525 int64_t Value = CE->getValue();
526 return Value > 0 && Value < 33;
528 bool isImm0_65535() const {
529 if (Kind != Immediate)
531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532 if (!CE) return false;
533 int64_t Value = CE->getValue();
534 return Value >= 0 && Value < 65536;
536 bool isImm0_65535Expr() const {
537 if (Kind != Immediate)
539 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
540 // If it's not a constant expression, it'll generate a fixup and be
542 if (!CE) return true;
543 int64_t Value = CE->getValue();
544 return Value >= 0 && Value < 65536;
546 bool isImm24bit() const {
547 if (Kind != Immediate)
549 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
550 if (!CE) return false;
551 int64_t Value = CE->getValue();
552 return Value >= 0 && Value <= 0xffffff;
554 bool isImmThumbSR() const {
555 if (Kind != Immediate)
557 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
558 if (!CE) return false;
559 int64_t Value = CE->getValue();
560 return Value > 0 && Value < 33;
562 bool isPKHLSLImm() const {
563 if (Kind != Immediate)
565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
566 if (!CE) return false;
567 int64_t Value = CE->getValue();
568 return Value >= 0 && Value < 32;
570 bool isPKHASRImm() const {
571 if (Kind != Immediate)
573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574 if (!CE) return false;
575 int64_t Value = CE->getValue();
576 return Value > 0 && Value <= 32;
578 bool isARMSOImm() const {
579 if (Kind != Immediate)
581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582 if (!CE) return false;
583 int64_t Value = CE->getValue();
584 return ARM_AM::getSOImmVal(Value) != -1;
586 bool isT2SOImm() const {
587 if (Kind != Immediate)
589 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
590 if (!CE) return false;
591 int64_t Value = CE->getValue();
592 return ARM_AM::getT2SOImmVal(Value) != -1;
594 bool isSetEndImm() const {
595 if (Kind != Immediate)
597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
598 if (!CE) return false;
599 int64_t Value = CE->getValue();
600 return Value == 1 || Value == 0;
602 bool isReg() const { return Kind == Register; }
603 bool isRegList() const { return Kind == RegisterList; }
604 bool isDPRRegList() const { return Kind == DPRRegisterList; }
605 bool isSPRRegList() const { return Kind == SPRRegisterList; }
606 bool isToken() const { return Kind == Token; }
607 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
608 bool isMemory() const { return Kind == Memory; }
609 bool isShifterImm() const { return Kind == ShifterImmediate; }
610 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
611 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
612 bool isRotImm() const { return Kind == RotateImmediate; }
613 bool isBitfield() const { return Kind == BitfieldDescriptor; }
614 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
615 bool isPostIdxReg() const {
616 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
618 bool isMemNoOffset() const {
621 // No offset of any kind.
622 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
624 bool isAddrMode2() const {
627 // Check for register offset.
628 if (Mem.OffsetRegNum) return true;
629 // Immediate offset in range [-4095, 4095].
630 if (!Mem.OffsetImm) return true;
631 int64_t Val = Mem.OffsetImm->getValue();
632 return Val > -4096 && Val < 4096;
634 bool isAM2OffsetImm() const {
635 if (Kind != Immediate)
637 // Immediate offset in range [-4095, 4095].
638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639 if (!CE) return false;
640 int64_t Val = CE->getValue();
641 return Val > -4096 && Val < 4096;
643 bool isAddrMode3() const {
646 // No shifts are legal for AM3.
647 if (Mem.ShiftType != ARM_AM::no_shift) return false;
648 // Check for register offset.
649 if (Mem.OffsetRegNum) return true;
650 // Immediate offset in range [-255, 255].
651 if (!Mem.OffsetImm) return true;
652 int64_t Val = Mem.OffsetImm->getValue();
653 return Val > -256 && Val < 256;
655 bool isAM3Offset() const {
656 if (Kind != Immediate && Kind != PostIndexRegister)
658 if (Kind == PostIndexRegister)
659 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
660 // Immediate offset in range [-255, 255].
661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662 if (!CE) return false;
663 int64_t Val = CE->getValue();
664 // Special case, #-0 is INT32_MIN.
665 return (Val > -256 && Val < 256) || Val == INT32_MIN;
667 bool isAddrMode5() const {
670 // Check for register offset.
671 if (Mem.OffsetRegNum) return false;
672 // Immediate offset in range [-1020, 1020] and a multiple of 4.
673 if (!Mem.OffsetImm) return true;
674 int64_t Val = Mem.OffsetImm->getValue();
675 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
678 bool isMemRegOffset() const {
679 if (Kind != Memory || !Mem.OffsetRegNum)
683 bool isT2MemRegOffset() const {
684 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
686 // Only lsl #{0, 1, 2, 3} allowed.
687 if (Mem.ShiftType == ARM_AM::no_shift)
689 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
693 bool isMemThumbRR() const {
694 // Thumb reg+reg addressing is simple. Just two registers, a base and
695 // an offset. No shifts, negations or any other complicating factors.
696 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
697 Mem.ShiftType != ARM_AM::no_shift)
699 return isARMLowRegister(Mem.BaseRegNum) &&
700 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
702 bool isMemThumbRIs4() const {
703 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
704 !isARMLowRegister(Mem.BaseRegNum))
706 // Immediate offset, multiple of 4 in range [0, 124].
707 if (!Mem.OffsetImm) return true;
708 int64_t Val = Mem.OffsetImm->getValue();
709 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
711 bool isMemThumbRIs2() const {
712 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
713 !isARMLowRegister(Mem.BaseRegNum))
715 // Immediate offset, multiple of 4 in range [0, 62].
716 if (!Mem.OffsetImm) return true;
717 int64_t Val = Mem.OffsetImm->getValue();
718 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
720 bool isMemThumbRIs1() const {
721 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
722 !isARMLowRegister(Mem.BaseRegNum))
724 // Immediate offset in range [0, 31].
725 if (!Mem.OffsetImm) return true;
726 int64_t Val = Mem.OffsetImm->getValue();
727 return Val >= 0 && Val <= 31;
729 bool isMemThumbSPI() const {
730 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
732 // Immediate offset, multiple of 4 in range [0, 1020].
733 if (!Mem.OffsetImm) return true;
734 int64_t Val = Mem.OffsetImm->getValue();
735 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
737 bool isMemImm8Offset() const {
738 if (Kind != Memory || Mem.OffsetRegNum != 0)
740 // Immediate offset in range [-255, 255].
741 if (!Mem.OffsetImm) return true;
742 int64_t Val = Mem.OffsetImm->getValue();
743 return Val > -256 && Val < 256;
745 bool isMemNegImm8Offset() const {
746 if (Kind != Memory || Mem.OffsetRegNum != 0)
748 // Immediate offset in range [-255, -1].
749 if (!Mem.OffsetImm) return true;
750 int64_t Val = Mem.OffsetImm->getValue();
751 return Val > -256 && Val < 0;
753 bool isMemUImm12Offset() const {
754 // If we have an immediate that's not a constant, treat it as a label
755 // reference needing a fixup. If it is a constant, it's something else
757 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
760 if (Kind != Memory || Mem.OffsetRegNum != 0)
762 // Immediate offset in range [0, 4095].
763 if (!Mem.OffsetImm) return true;
764 int64_t Val = Mem.OffsetImm->getValue();
765 return (Val >= 0 && Val < 4096);
767 bool isMemImm12Offset() const {
768 // If we have an immediate that's not a constant, treat it as a label
769 // reference needing a fixup. If it is a constant, it's something else
771 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
774 if (Kind != Memory || Mem.OffsetRegNum != 0)
776 // Immediate offset in range [-4095, 4095].
777 if (!Mem.OffsetImm) return true;
778 int64_t Val = Mem.OffsetImm->getValue();
779 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
781 bool isPostIdxImm8() const {
782 if (Kind != Immediate)
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Val = CE->getValue();
787 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
790 bool isMSRMask() const { return Kind == MSRMask; }
791 bool isProcIFlags() const { return Kind == ProcIFlags; }
793 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
794 // Add as immediates when possible. Null MCExpr = 0.
796 Inst.addOperand(MCOperand::CreateImm(0));
797 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
798 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
800 Inst.addOperand(MCOperand::CreateExpr(Expr));
803 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
804 assert(N == 2 && "Invalid number of operands!");
805 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
806 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
807 Inst.addOperand(MCOperand::CreateReg(RegNum));
810 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
811 assert(N == 1 && "Invalid number of operands!");
812 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
815 void addITMaskOperands(MCInst &Inst, unsigned N) const {
816 assert(N == 1 && "Invalid number of operands!");
817 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
820 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
821 assert(N == 1 && "Invalid number of operands!");
822 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
825 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
826 assert(N == 1 && "Invalid number of operands!");
827 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
830 void addCCOutOperands(MCInst &Inst, unsigned N) const {
831 assert(N == 1 && "Invalid number of operands!");
832 Inst.addOperand(MCOperand::CreateReg(getReg()));
835 void addRegOperands(MCInst &Inst, unsigned N) const {
836 assert(N == 1 && "Invalid number of operands!");
837 Inst.addOperand(MCOperand::CreateReg(getReg()));
840 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
841 assert(N == 3 && "Invalid number of operands!");
842 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
843 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
844 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
845 Inst.addOperand(MCOperand::CreateImm(
846 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
849 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
850 assert(N == 2 && "Invalid number of operands!");
851 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
852 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
853 Inst.addOperand(MCOperand::CreateImm(
854 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
857 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
858 assert(N == 1 && "Invalid number of operands!");
859 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
863 void addRegListOperands(MCInst &Inst, unsigned N) const {
864 assert(N == 1 && "Invalid number of operands!");
865 const SmallVectorImpl<unsigned> &RegList = getRegList();
866 for (SmallVectorImpl<unsigned>::const_iterator
867 I = RegList.begin(), E = RegList.end(); I != E; ++I)
868 Inst.addOperand(MCOperand::CreateReg(*I));
871 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
872 addRegListOperands(Inst, N);
875 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
876 addRegListOperands(Inst, N);
879 void addRotImmOperands(MCInst &Inst, unsigned N) const {
880 assert(N == 1 && "Invalid number of operands!");
881 // Encoded as val>>3. The printer handles display as 8, 16, 24.
882 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
885 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
886 assert(N == 1 && "Invalid number of operands!");
887 // Munge the lsb/width into a bitfield mask.
888 unsigned lsb = Bitfield.LSB;
889 unsigned width = Bitfield.Width;
890 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
891 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
892 (32 - (lsb + width)));
893 Inst.addOperand(MCOperand::CreateImm(Mask));
896 void addImmOperands(MCInst &Inst, unsigned N) const {
897 assert(N == 1 && "Invalid number of operands!");
898 addExpr(Inst, getImm());
901 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
902 assert(N == 1 && "Invalid number of operands!");
903 // The immediate is scaled by four in the encoding and is stored
904 // in the MCInst as such. Lop off the low two bits here.
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
909 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
910 assert(N == 1 && "Invalid number of operands!");
911 // The immediate is scaled by four in the encoding and is stored
912 // in the MCInst as such. Lop off the low two bits here.
913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
914 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
917 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
918 assert(N == 1 && "Invalid number of operands!");
919 addExpr(Inst, getImm());
922 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
923 assert(N == 1 && "Invalid number of operands!");
924 addExpr(Inst, getImm());
927 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
928 assert(N == 1 && "Invalid number of operands!");
929 addExpr(Inst, getImm());
932 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
933 assert(N == 1 && "Invalid number of operands!");
934 addExpr(Inst, getImm());
937 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
938 assert(N == 1 && "Invalid number of operands!");
939 // The constant encodes as the immediate-1, and we store in the instruction
940 // the bits as encoded, so subtract off one here.
941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
945 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
946 assert(N == 1 && "Invalid number of operands!");
947 // The constant encodes as the immediate-1, and we store in the instruction
948 // the bits as encoded, so subtract off one here.
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
953 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
954 assert(N == 1 && "Invalid number of operands!");
955 addExpr(Inst, getImm());
958 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
959 assert(N == 1 && "Invalid number of operands!");
960 addExpr(Inst, getImm());
963 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
964 assert(N == 1 && "Invalid number of operands!");
965 addExpr(Inst, getImm());
968 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
969 assert(N == 1 && "Invalid number of operands!");
970 // The constant encodes as the immediate, except for 32, which encodes as
972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973 unsigned Imm = CE->getValue();
974 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
977 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
978 assert(N == 1 && "Invalid number of operands!");
979 addExpr(Inst, getImm());
982 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
983 assert(N == 1 && "Invalid number of operands!");
984 // An ASR value of 32 encodes as 0, so that's how we want to add it to
985 // the instruction as well.
986 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
987 int Val = CE->getValue();
988 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
991 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
992 assert(N == 1 && "Invalid number of operands!");
993 addExpr(Inst, getImm());
996 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
997 assert(N == 1 && "Invalid number of operands!");
998 addExpr(Inst, getImm());
1001 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1002 assert(N == 1 && "Invalid number of operands!");
1003 addExpr(Inst, getImm());
1006 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1007 assert(N == 1 && "Invalid number of operands!");
1008 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1011 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1012 assert(N == 1 && "Invalid number of operands!");
1013 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1016 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1017 assert(N == 3 && "Invalid number of operands!");
1018 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1019 if (!Mem.OffsetRegNum) {
1020 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1021 // Special case for #-0
1022 if (Val == INT32_MIN) Val = 0;
1023 if (Val < 0) Val = -Val;
1024 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1026 // For register offset, we encode the shift type and negation flag
1028 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1029 Mem.ShiftImm, Mem.ShiftType);
1031 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1032 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1033 Inst.addOperand(MCOperand::CreateImm(Val));
1036 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1037 assert(N == 2 && "Invalid number of operands!");
1038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1039 assert(CE && "non-constant AM2OffsetImm operand!");
1040 int32_t Val = CE->getValue();
1041 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1042 // Special case for #-0
1043 if (Val == INT32_MIN) Val = 0;
1044 if (Val < 0) Val = -Val;
1045 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1046 Inst.addOperand(MCOperand::CreateReg(0));
1047 Inst.addOperand(MCOperand::CreateImm(Val));
1050 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1051 assert(N == 3 && "Invalid number of operands!");
1052 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1053 if (!Mem.OffsetRegNum) {
1054 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1055 // Special case for #-0
1056 if (Val == INT32_MIN) Val = 0;
1057 if (Val < 0) Val = -Val;
1058 Val = ARM_AM::getAM3Opc(AddSub, Val);
1060 // For register offset, we encode the shift type and negation flag
1062 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1064 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1065 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1066 Inst.addOperand(MCOperand::CreateImm(Val));
1069 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1070 assert(N == 2 && "Invalid number of operands!");
1071 if (Kind == PostIndexRegister) {
1073 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1074 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1075 Inst.addOperand(MCOperand::CreateImm(Val));
1080 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1081 int32_t Val = CE->getValue();
1082 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1083 // Special case for #-0
1084 if (Val == INT32_MIN) Val = 0;
1085 if (Val < 0) Val = -Val;
1086 Val = ARM_AM::getAM3Opc(AddSub, Val);
1087 Inst.addOperand(MCOperand::CreateReg(0));
1088 Inst.addOperand(MCOperand::CreateImm(Val));
1091 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1092 assert(N == 2 && "Invalid number of operands!");
1093 // The lower two bits are always zero and as such are not encoded.
1094 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1095 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1096 // Special case for #-0
1097 if (Val == INT32_MIN) Val = 0;
1098 if (Val < 0) Val = -Val;
1099 Val = ARM_AM::getAM5Opc(AddSub, Val);
1100 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1101 Inst.addOperand(MCOperand::CreateImm(Val));
1104 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1105 assert(N == 2 && "Invalid number of operands!");
1106 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1107 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1108 Inst.addOperand(MCOperand::CreateImm(Val));
1111 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1112 assert(N == 2 && "Invalid number of operands!");
1113 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1114 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1115 Inst.addOperand(MCOperand::CreateImm(Val));
1118 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1119 assert(N == 2 && "Invalid number of operands!");
1120 // If this is an immediate, it's a label reference.
1121 if (Kind == Immediate) {
1122 addExpr(Inst, getImm());
1123 Inst.addOperand(MCOperand::CreateImm(0));
1127 // Otherwise, it's a normal memory reg+offset.
1128 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1129 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1130 Inst.addOperand(MCOperand::CreateImm(Val));
1133 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1134 assert(N == 2 && "Invalid number of operands!");
1135 // If this is an immediate, it's a label reference.
1136 if (Kind == Immediate) {
1137 addExpr(Inst, getImm());
1138 Inst.addOperand(MCOperand::CreateImm(0));
1142 // Otherwise, it's a normal memory reg+offset.
1143 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1144 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1145 Inst.addOperand(MCOperand::CreateImm(Val));
1148 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1149 assert(N == 3 && "Invalid number of operands!");
1150 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1151 Mem.ShiftImm, Mem.ShiftType);
1152 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1153 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1154 Inst.addOperand(MCOperand::CreateImm(Val));
1157 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1158 assert(N == 3 && "Invalid number of operands!");
1159 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1160 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1161 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1164 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1165 assert(N == 2 && "Invalid number of operands!");
1166 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1167 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1170 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1171 assert(N == 2 && "Invalid number of operands!");
1172 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1173 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1174 Inst.addOperand(MCOperand::CreateImm(Val));
1177 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1178 assert(N == 2 && "Invalid number of operands!");
1179 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1180 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1181 Inst.addOperand(MCOperand::CreateImm(Val));
1184 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1185 assert(N == 2 && "Invalid number of operands!");
1186 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1187 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1188 Inst.addOperand(MCOperand::CreateImm(Val));
1191 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1192 assert(N == 2 && "Invalid number of operands!");
1193 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1194 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1195 Inst.addOperand(MCOperand::CreateImm(Val));
1198 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1199 assert(N == 1 && "Invalid number of operands!");
1200 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1201 assert(CE && "non-constant post-idx-imm8 operand!");
1202 int Imm = CE->getValue();
1203 bool isAdd = Imm >= 0;
1204 if (Imm == INT32_MIN) Imm = 0;
1205 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1206 Inst.addOperand(MCOperand::CreateImm(Imm));
1209 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1210 assert(N == 2 && "Invalid number of operands!");
1211 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1212 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1215 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1216 assert(N == 2 && "Invalid number of operands!");
1217 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1218 // The sign, shift type, and shift amount are encoded in a single operand
1219 // using the AM2 encoding helpers.
1220 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1221 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1222 PostIdxReg.ShiftTy);
1223 Inst.addOperand(MCOperand::CreateImm(Imm));
1226 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1227 assert(N == 1 && "Invalid number of operands!");
1228 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1231 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1232 assert(N == 1 && "Invalid number of operands!");
1233 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1236 virtual void print(raw_ostream &OS) const;
1238 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1239 ARMOperand *Op = new ARMOperand(ITCondMask);
1240 Op->ITMask.Mask = Mask;
1246 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1247 ARMOperand *Op = new ARMOperand(CondCode);
1254 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1255 ARMOperand *Op = new ARMOperand(CoprocNum);
1256 Op->Cop.Val = CopVal;
1262 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1263 ARMOperand *Op = new ARMOperand(CoprocReg);
1264 Op->Cop.Val = CopVal;
1270 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1271 ARMOperand *Op = new ARMOperand(CCOut);
1272 Op->Reg.RegNum = RegNum;
1278 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1279 ARMOperand *Op = new ARMOperand(Token);
1280 Op->Tok.Data = Str.data();
1281 Op->Tok.Length = Str.size();
1287 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1288 ARMOperand *Op = new ARMOperand(Register);
1289 Op->Reg.RegNum = RegNum;
1295 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1300 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1301 Op->RegShiftedReg.ShiftTy = ShTy;
1302 Op->RegShiftedReg.SrcReg = SrcReg;
1303 Op->RegShiftedReg.ShiftReg = ShiftReg;
1304 Op->RegShiftedReg.ShiftImm = ShiftImm;
1310 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1314 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1315 Op->RegShiftedImm.ShiftTy = ShTy;
1316 Op->RegShiftedImm.SrcReg = SrcReg;
1317 Op->RegShiftedImm.ShiftImm = ShiftImm;
1323 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1325 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1326 Op->ShifterImm.isASR = isASR;
1327 Op->ShifterImm.Imm = Imm;
1333 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1334 ARMOperand *Op = new ARMOperand(RotateImmediate);
1335 Op->RotImm.Imm = Imm;
1341 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1343 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1344 Op->Bitfield.LSB = LSB;
1345 Op->Bitfield.Width = Width;
1352 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1353 SMLoc StartLoc, SMLoc EndLoc) {
1354 KindTy Kind = RegisterList;
1356 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1357 contains(Regs.front().first))
1358 Kind = DPRRegisterList;
1359 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1360 contains(Regs.front().first))
1361 Kind = SPRRegisterList;
1363 ARMOperand *Op = new ARMOperand(Kind);
1364 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1365 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1366 Op->Registers.push_back(I->first);
1367 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1368 Op->StartLoc = StartLoc;
1369 Op->EndLoc = EndLoc;
1373 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1374 ARMOperand *Op = new ARMOperand(Immediate);
1381 static ARMOperand *CreateMem(unsigned BaseRegNum,
1382 const MCConstantExpr *OffsetImm,
1383 unsigned OffsetRegNum,
1384 ARM_AM::ShiftOpc ShiftType,
1388 ARMOperand *Op = new ARMOperand(Memory);
1389 Op->Mem.BaseRegNum = BaseRegNum;
1390 Op->Mem.OffsetImm = OffsetImm;
1391 Op->Mem.OffsetRegNum = OffsetRegNum;
1392 Op->Mem.ShiftType = ShiftType;
1393 Op->Mem.ShiftImm = ShiftImm;
1394 Op->Mem.isNegative = isNegative;
1400 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1401 ARM_AM::ShiftOpc ShiftTy,
1404 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1405 Op->PostIdxReg.RegNum = RegNum;
1406 Op->PostIdxReg.isAdd = isAdd;
1407 Op->PostIdxReg.ShiftTy = ShiftTy;
1408 Op->PostIdxReg.ShiftImm = ShiftImm;
1414 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1415 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1416 Op->MBOpt.Val = Opt;
1422 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1423 ARMOperand *Op = new ARMOperand(ProcIFlags);
1424 Op->IFlags.Val = IFlags;
1430 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1431 ARMOperand *Op = new ARMOperand(MSRMask);
1432 Op->MMask.Val = MMask;
1439 } // end anonymous namespace.
1441 void ARMOperand::print(raw_ostream &OS) const {
1444 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1447 OS << "<ccout " << getReg() << ">";
1450 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1451 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1453 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1454 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1458 OS << "<coprocessor number: " << getCoproc() << ">";
1461 OS << "<coprocessor register: " << getCoproc() << ">";
1464 OS << "<mask: " << getMSRMask() << ">";
1467 getImm()->print(OS);
1470 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1474 << " base:" << Mem.BaseRegNum;
1477 case PostIndexRegister:
1478 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1479 << PostIdxReg.RegNum;
1480 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1481 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1482 << PostIdxReg.ShiftImm;
1486 OS << "<ARM_PROC::";
1487 unsigned IFlags = getProcIFlags();
1488 for (int i=2; i >= 0; --i)
1489 if (IFlags & (1 << i))
1490 OS << ARM_PROC::IFlagsToString(1 << i);
1495 OS << "<register " << getReg() << ">";
1497 case ShifterImmediate:
1498 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1499 << " #" << ShifterImm.Imm << ">";
1501 case ShiftedRegister:
1502 OS << "<so_reg_reg "
1503 << RegShiftedReg.SrcReg
1504 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1505 << ", " << RegShiftedReg.ShiftReg << ", "
1506 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1509 case ShiftedImmediate:
1510 OS << "<so_reg_imm "
1511 << RegShiftedImm.SrcReg
1512 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1513 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1516 case RotateImmediate:
1517 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1519 case BitfieldDescriptor:
1520 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1521 << ", width: " << Bitfield.Width << ">";
1524 case DPRRegisterList:
1525 case SPRRegisterList: {
1526 OS << "<register_list ";
1528 const SmallVectorImpl<unsigned> &RegList = getRegList();
1529 for (SmallVectorImpl<unsigned>::const_iterator
1530 I = RegList.begin(), E = RegList.end(); I != E; ) {
1532 if (++I < E) OS << ", ";
1539 OS << "'" << getToken() << "'";
1544 /// @name Auto-generated Match Functions
1547 static unsigned MatchRegisterName(StringRef Name);
1551 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1552 SMLoc &StartLoc, SMLoc &EndLoc) {
1553 RegNo = tryParseRegister();
1555 return (RegNo == (unsigned)-1);
1558 /// Try to parse a register name. The token must be an Identifier when called,
1559 /// and if it is a register name the token is eaten and the register number is
1560 /// returned. Otherwise return -1.
1562 int ARMAsmParser::tryParseRegister() {
1563 const AsmToken &Tok = Parser.getTok();
1564 if (Tok.isNot(AsmToken::Identifier)) return -1;
1566 // FIXME: Validate register for the current architecture; we have to do
1567 // validation later, so maybe there is no need for this here.
1568 std::string upperCase = Tok.getString().str();
1569 std::string lowerCase = LowercaseString(upperCase);
1570 unsigned RegNum = MatchRegisterName(lowerCase);
1572 RegNum = StringSwitch<unsigned>(lowerCase)
1573 .Case("r13", ARM::SP)
1574 .Case("r14", ARM::LR)
1575 .Case("r15", ARM::PC)
1576 .Case("ip", ARM::R12)
1579 if (!RegNum) return -1;
1581 Parser.Lex(); // Eat identifier token.
1585 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1586 // If a recoverable error occurs, return 1. If an irrecoverable error
1587 // occurs, return -1. An irrecoverable error is one where tokens have been
1588 // consumed in the process of trying to parse the shifter (i.e., when it is
1589 // indeed a shifter operand, but malformed).
1590 int ARMAsmParser::tryParseShiftRegister(
1591 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1592 SMLoc S = Parser.getTok().getLoc();
1593 const AsmToken &Tok = Parser.getTok();
1594 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1596 std::string upperCase = Tok.getString().str();
1597 std::string lowerCase = LowercaseString(upperCase);
1598 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1599 .Case("lsl", ARM_AM::lsl)
1600 .Case("lsr", ARM_AM::lsr)
1601 .Case("asr", ARM_AM::asr)
1602 .Case("ror", ARM_AM::ror)
1603 .Case("rrx", ARM_AM::rrx)
1604 .Default(ARM_AM::no_shift);
1606 if (ShiftTy == ARM_AM::no_shift)
1609 Parser.Lex(); // Eat the operator.
1611 // The source register for the shift has already been added to the
1612 // operand list, so we need to pop it off and combine it into the shifted
1613 // register operand instead.
1614 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1615 if (!PrevOp->isReg())
1616 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1617 int SrcReg = PrevOp->getReg();
1620 if (ShiftTy == ARM_AM::rrx) {
1621 // RRX Doesn't have an explicit shift amount. The encoder expects
1622 // the shift register to be the same as the source register. Seems odd,
1626 // Figure out if this is shifted by a constant or a register (for non-RRX).
1627 if (Parser.getTok().is(AsmToken::Hash)) {
1628 Parser.Lex(); // Eat hash.
1629 SMLoc ImmLoc = Parser.getTok().getLoc();
1630 const MCExpr *ShiftExpr = 0;
1631 if (getParser().ParseExpression(ShiftExpr)) {
1632 Error(ImmLoc, "invalid immediate shift value");
1635 // The expression must be evaluatable as an immediate.
1636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1638 Error(ImmLoc, "invalid immediate shift value");
1641 // Range check the immediate.
1642 // lsl, ror: 0 <= imm <= 31
1643 // lsr, asr: 0 <= imm <= 32
1644 Imm = CE->getValue();
1646 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1647 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1648 Error(ImmLoc, "immediate shift value out of range");
1651 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1652 ShiftReg = tryParseRegister();
1653 SMLoc L = Parser.getTok().getLoc();
1654 if (ShiftReg == -1) {
1655 Error (L, "expected immediate or register in shift operand");
1659 Error (Parser.getTok().getLoc(),
1660 "expected immediate or register in shift operand");
1665 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1666 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1668 S, Parser.getTok().getLoc()));
1670 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1671 S, Parser.getTok().getLoc()));
1677 /// Try to parse a register name. The token must be an Identifier when called.
1678 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1679 /// if there is a "writeback". 'true' if it's not a register.
1681 /// TODO this is likely to change to allow different register types and or to
1682 /// parse for a specific register type.
1684 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1685 SMLoc S = Parser.getTok().getLoc();
1686 int RegNo = tryParseRegister();
1690 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1692 const AsmToken &ExclaimTok = Parser.getTok();
1693 if (ExclaimTok.is(AsmToken::Exclaim)) {
1694 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1695 ExclaimTok.getLoc()));
1696 Parser.Lex(); // Eat exclaim token
1702 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1703 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1705 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1706 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1708 switch (Name.size()) {
1711 if (Name[0] != CoprocOp)
1728 if (Name[0] != CoprocOp || Name[1] != '1')
1732 case '0': return 10;
1733 case '1': return 11;
1734 case '2': return 12;
1735 case '3': return 13;
1736 case '4': return 14;
1737 case '5': return 15;
1745 /// parseITCondCode - Try to parse a condition code for an IT instruction.
1746 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1747 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1748 SMLoc S = Parser.getTok().getLoc();
1749 const AsmToken &Tok = Parser.getTok();
1750 if (!Tok.is(AsmToken::Identifier))
1751 return MatchOperand_NoMatch;
1752 unsigned CC = StringSwitch<unsigned>(Tok.getString())
1753 .Case("eq", ARMCC::EQ)
1754 .Case("ne", ARMCC::NE)
1755 .Case("hs", ARMCC::HS)
1756 .Case("cs", ARMCC::HS)
1757 .Case("lo", ARMCC::LO)
1758 .Case("cc", ARMCC::LO)
1759 .Case("mi", ARMCC::MI)
1760 .Case("pl", ARMCC::PL)
1761 .Case("vs", ARMCC::VS)
1762 .Case("vc", ARMCC::VC)
1763 .Case("hi", ARMCC::HI)
1764 .Case("ls", ARMCC::LS)
1765 .Case("ge", ARMCC::GE)
1766 .Case("lt", ARMCC::LT)
1767 .Case("gt", ARMCC::GT)
1768 .Case("le", ARMCC::LE)
1769 .Case("al", ARMCC::AL)
1772 return MatchOperand_NoMatch;
1773 Parser.Lex(); // Eat the token.
1775 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1777 return MatchOperand_Success;
1780 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1781 /// token must be an Identifier when called, and if it is a coprocessor
1782 /// number, the token is eaten and the operand is added to the operand list.
1783 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1784 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1785 SMLoc S = Parser.getTok().getLoc();
1786 const AsmToken &Tok = Parser.getTok();
1787 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1789 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1791 return MatchOperand_NoMatch;
1793 Parser.Lex(); // Eat identifier token.
1794 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1795 return MatchOperand_Success;
1798 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1799 /// token must be an Identifier when called, and if it is a coprocessor
1800 /// number, the token is eaten and the operand is added to the operand list.
1801 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1802 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1803 SMLoc S = Parser.getTok().getLoc();
1804 const AsmToken &Tok = Parser.getTok();
1805 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1807 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1809 return MatchOperand_NoMatch;
1811 Parser.Lex(); // Eat identifier token.
1812 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1813 return MatchOperand_Success;
1816 /// Parse a register list, return it if successful else return null. The first
1817 /// token must be a '{' when called.
1819 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1820 assert(Parser.getTok().is(AsmToken::LCurly) &&
1821 "Token is not a Left Curly Brace");
1822 SMLoc S = Parser.getTok().getLoc();
1824 // Read the rest of the registers in the list.
1825 unsigned PrevRegNum = 0;
1826 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1829 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1830 Parser.Lex(); // Eat non-identifier token.
1832 const AsmToken &RegTok = Parser.getTok();
1833 SMLoc RegLoc = RegTok.getLoc();
1834 if (RegTok.isNot(AsmToken::Identifier)) {
1835 Error(RegLoc, "register expected");
1839 int RegNum = tryParseRegister();
1841 Error(RegLoc, "register expected");
1846 int Reg = PrevRegNum;
1849 Registers.push_back(std::make_pair(Reg, RegLoc));
1850 } while (Reg != RegNum);
1852 Registers.push_back(std::make_pair(RegNum, RegLoc));
1855 PrevRegNum = RegNum;
1856 } while (Parser.getTok().is(AsmToken::Comma) ||
1857 Parser.getTok().is(AsmToken::Minus));
1859 // Process the right curly brace of the list.
1860 const AsmToken &RCurlyTok = Parser.getTok();
1861 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1862 Error(RCurlyTok.getLoc(), "'}' expected");
1866 SMLoc E = RCurlyTok.getLoc();
1867 Parser.Lex(); // Eat right curly brace token.
1869 // Verify the register list.
1870 bool EmittedWarning = false;
1871 unsigned HighRegNum = 0;
1872 BitVector RegMap(32);
1873 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
1874 const std::pair<unsigned, SMLoc> &RegInfo = Registers[i];
1875 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1878 Error(RegInfo.second, "register duplicated in register list");
1882 if (!EmittedWarning && Reg < HighRegNum)
1883 Warning(RegInfo.second,
1884 "register not in ascending order in register list");
1887 HighRegNum = std::max(Reg, HighRegNum);
1890 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1894 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1895 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1896 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1897 SMLoc S = Parser.getTok().getLoc();
1898 const AsmToken &Tok = Parser.getTok();
1899 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1900 StringRef OptStr = Tok.getString();
1902 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1903 .Case("sy", ARM_MB::SY)
1904 .Case("st", ARM_MB::ST)
1905 .Case("sh", ARM_MB::ISH)
1906 .Case("ish", ARM_MB::ISH)
1907 .Case("shst", ARM_MB::ISHST)
1908 .Case("ishst", ARM_MB::ISHST)
1909 .Case("nsh", ARM_MB::NSH)
1910 .Case("un", ARM_MB::NSH)
1911 .Case("nshst", ARM_MB::NSHST)
1912 .Case("unst", ARM_MB::NSHST)
1913 .Case("osh", ARM_MB::OSH)
1914 .Case("oshst", ARM_MB::OSHST)
1918 return MatchOperand_NoMatch;
1920 Parser.Lex(); // Eat identifier token.
1921 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1922 return MatchOperand_Success;
1925 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1926 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1927 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1928 SMLoc S = Parser.getTok().getLoc();
1929 const AsmToken &Tok = Parser.getTok();
1930 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1931 StringRef IFlagsStr = Tok.getString();
1933 unsigned IFlags = 0;
1934 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1935 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1936 .Case("a", ARM_PROC::A)
1937 .Case("i", ARM_PROC::I)
1938 .Case("f", ARM_PROC::F)
1941 // If some specific iflag is already set, it means that some letter is
1942 // present more than once, this is not acceptable.
1943 if (Flag == ~0U || (IFlags & Flag))
1944 return MatchOperand_NoMatch;
1949 Parser.Lex(); // Eat identifier token.
1950 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1951 return MatchOperand_Success;
1954 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1955 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1956 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1957 SMLoc S = Parser.getTok().getLoc();
1958 const AsmToken &Tok = Parser.getTok();
1959 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1960 StringRef Mask = Tok.getString();
1962 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1963 size_t Start = 0, Next = Mask.find('_');
1964 StringRef Flags = "";
1965 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1966 if (Next != StringRef::npos)
1967 Flags = Mask.slice(Next+1, Mask.size());
1969 // FlagsVal contains the complete mask:
1971 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1972 unsigned FlagsVal = 0;
1974 if (SpecReg == "apsr") {
1975 FlagsVal = StringSwitch<unsigned>(Flags)
1976 .Case("nzcvq", 0x8) // same as CPSR_f
1977 .Case("g", 0x4) // same as CPSR_s
1978 .Case("nzcvqg", 0xc) // same as CPSR_fs
1981 if (FlagsVal == ~0U) {
1983 return MatchOperand_NoMatch;
1985 FlagsVal = 0; // No flag
1987 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1988 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1990 for (int i = 0, e = Flags.size(); i != e; ++i) {
1991 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1998 // If some specific flag is already set, it means that some letter is
1999 // present more than once, this is not acceptable.
2000 if (FlagsVal == ~0U || (FlagsVal & Flag))
2001 return MatchOperand_NoMatch;
2004 } else // No match for special register.
2005 return MatchOperand_NoMatch;
2007 // Special register without flags are equivalent to "fc" flags.
2011 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2012 if (SpecReg == "spsr")
2015 Parser.Lex(); // Eat identifier token.
2016 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2017 return MatchOperand_Success;
2020 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2021 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2022 int Low, int High) {
2023 const AsmToken &Tok = Parser.getTok();
2024 if (Tok.isNot(AsmToken::Identifier)) {
2025 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2026 return MatchOperand_ParseFail;
2028 StringRef ShiftName = Tok.getString();
2029 std::string LowerOp = LowercaseString(Op);
2030 std::string UpperOp = UppercaseString(Op);
2031 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2032 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2033 return MatchOperand_ParseFail;
2035 Parser.Lex(); // Eat shift type token.
2037 // There must be a '#' and a shift amount.
2038 if (Parser.getTok().isNot(AsmToken::Hash)) {
2039 Error(Parser.getTok().getLoc(), "'#' expected");
2040 return MatchOperand_ParseFail;
2042 Parser.Lex(); // Eat hash token.
2044 const MCExpr *ShiftAmount;
2045 SMLoc Loc = Parser.getTok().getLoc();
2046 if (getParser().ParseExpression(ShiftAmount)) {
2047 Error(Loc, "illegal expression");
2048 return MatchOperand_ParseFail;
2050 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2052 Error(Loc, "constant expression expected");
2053 return MatchOperand_ParseFail;
2055 int Val = CE->getValue();
2056 if (Val < Low || Val > High) {
2057 Error(Loc, "immediate value out of range");
2058 return MatchOperand_ParseFail;
2061 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2063 return MatchOperand_Success;
2066 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2067 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2068 const AsmToken &Tok = Parser.getTok();
2069 SMLoc S = Tok.getLoc();
2070 if (Tok.isNot(AsmToken::Identifier)) {
2071 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2072 return MatchOperand_ParseFail;
2074 int Val = StringSwitch<int>(Tok.getString())
2078 Parser.Lex(); // Eat the token.
2081 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2082 return MatchOperand_ParseFail;
2084 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2086 S, Parser.getTok().getLoc()));
2087 return MatchOperand_Success;
2090 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2091 /// instructions. Legal values are:
2092 /// lsl #n 'n' in [0,31]
2093 /// asr #n 'n' in [1,32]
2094 /// n == 32 encoded as n == 0.
2095 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2096 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2097 const AsmToken &Tok = Parser.getTok();
2098 SMLoc S = Tok.getLoc();
2099 if (Tok.isNot(AsmToken::Identifier)) {
2100 Error(S, "shift operator 'asr' or 'lsl' expected");
2101 return MatchOperand_ParseFail;
2103 StringRef ShiftName = Tok.getString();
2105 if (ShiftName == "lsl" || ShiftName == "LSL")
2107 else if (ShiftName == "asr" || ShiftName == "ASR")
2110 Error(S, "shift operator 'asr' or 'lsl' expected");
2111 return MatchOperand_ParseFail;
2113 Parser.Lex(); // Eat the operator.
2115 // A '#' and a shift amount.
2116 if (Parser.getTok().isNot(AsmToken::Hash)) {
2117 Error(Parser.getTok().getLoc(), "'#' expected");
2118 return MatchOperand_ParseFail;
2120 Parser.Lex(); // Eat hash token.
2122 const MCExpr *ShiftAmount;
2123 SMLoc E = Parser.getTok().getLoc();
2124 if (getParser().ParseExpression(ShiftAmount)) {
2125 Error(E, "malformed shift expression");
2126 return MatchOperand_ParseFail;
2128 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2130 Error(E, "shift amount must be an immediate");
2131 return MatchOperand_ParseFail;
2134 int64_t Val = CE->getValue();
2136 // Shift amount must be in [1,32]
2137 if (Val < 1 || Val > 32) {
2138 Error(E, "'asr' shift amount must be in range [1,32]");
2139 return MatchOperand_ParseFail;
2141 // asr #32 encoded as asr #0.
2142 if (Val == 32) Val = 0;
2144 // Shift amount must be in [1,32]
2145 if (Val < 0 || Val > 31) {
2146 Error(E, "'lsr' shift amount must be in range [0,31]");
2147 return MatchOperand_ParseFail;
2151 E = Parser.getTok().getLoc();
2152 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2154 return MatchOperand_Success;
2157 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2158 /// of instructions. Legal values are:
2159 /// ror #n 'n' in {0, 8, 16, 24}
2160 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2161 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2162 const AsmToken &Tok = Parser.getTok();
2163 SMLoc S = Tok.getLoc();
2164 if (Tok.isNot(AsmToken::Identifier)) {
2165 Error(S, "rotate operator 'ror' expected");
2166 return MatchOperand_ParseFail;
2168 StringRef ShiftName = Tok.getString();
2169 if (ShiftName != "ror" && ShiftName != "ROR") {
2170 Error(S, "rotate operator 'ror' expected");
2171 return MatchOperand_ParseFail;
2173 Parser.Lex(); // Eat the operator.
2175 // A '#' and a rotate amount.
2176 if (Parser.getTok().isNot(AsmToken::Hash)) {
2177 Error(Parser.getTok().getLoc(), "'#' expected");
2178 return MatchOperand_ParseFail;
2180 Parser.Lex(); // Eat hash token.
2182 const MCExpr *ShiftAmount;
2183 SMLoc E = Parser.getTok().getLoc();
2184 if (getParser().ParseExpression(ShiftAmount)) {
2185 Error(E, "malformed rotate expression");
2186 return MatchOperand_ParseFail;
2188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2190 Error(E, "rotate amount must be an immediate");
2191 return MatchOperand_ParseFail;
2194 int64_t Val = CE->getValue();
2195 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2196 // normally, zero is represented in asm by omitting the rotate operand
2198 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2199 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2200 return MatchOperand_ParseFail;
2203 E = Parser.getTok().getLoc();
2204 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2206 return MatchOperand_Success;
2209 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2210 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2211 SMLoc S = Parser.getTok().getLoc();
2212 // The bitfield descriptor is really two operands, the LSB and the width.
2213 if (Parser.getTok().isNot(AsmToken::Hash)) {
2214 Error(Parser.getTok().getLoc(), "'#' expected");
2215 return MatchOperand_ParseFail;
2217 Parser.Lex(); // Eat hash token.
2219 const MCExpr *LSBExpr;
2220 SMLoc E = Parser.getTok().getLoc();
2221 if (getParser().ParseExpression(LSBExpr)) {
2222 Error(E, "malformed immediate expression");
2223 return MatchOperand_ParseFail;
2225 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2227 Error(E, "'lsb' operand must be an immediate");
2228 return MatchOperand_ParseFail;
2231 int64_t LSB = CE->getValue();
2232 // The LSB must be in the range [0,31]
2233 if (LSB < 0 || LSB > 31) {
2234 Error(E, "'lsb' operand must be in the range [0,31]");
2235 return MatchOperand_ParseFail;
2237 E = Parser.getTok().getLoc();
2239 // Expect another immediate operand.
2240 if (Parser.getTok().isNot(AsmToken::Comma)) {
2241 Error(Parser.getTok().getLoc(), "too few operands");
2242 return MatchOperand_ParseFail;
2244 Parser.Lex(); // Eat hash token.
2245 if (Parser.getTok().isNot(AsmToken::Hash)) {
2246 Error(Parser.getTok().getLoc(), "'#' expected");
2247 return MatchOperand_ParseFail;
2249 Parser.Lex(); // Eat hash token.
2251 const MCExpr *WidthExpr;
2252 if (getParser().ParseExpression(WidthExpr)) {
2253 Error(E, "malformed immediate expression");
2254 return MatchOperand_ParseFail;
2256 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2258 Error(E, "'width' operand must be an immediate");
2259 return MatchOperand_ParseFail;
2262 int64_t Width = CE->getValue();
2263 // The LSB must be in the range [1,32-lsb]
2264 if (Width < 1 || Width > 32 - LSB) {
2265 Error(E, "'width' operand must be in the range [1,32-lsb]");
2266 return MatchOperand_ParseFail;
2268 E = Parser.getTok().getLoc();
2270 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2272 return MatchOperand_Success;
2275 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2276 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2277 // Check for a post-index addressing register operand. Specifically:
2278 // postidx_reg := '+' register {, shift}
2279 // | '-' register {, shift}
2280 // | register {, shift}
2282 // This method must return MatchOperand_NoMatch without consuming any tokens
2283 // in the case where there is no match, as other alternatives take other
2285 AsmToken Tok = Parser.getTok();
2286 SMLoc S = Tok.getLoc();
2287 bool haveEaten = false;
2290 if (Tok.is(AsmToken::Plus)) {
2291 Parser.Lex(); // Eat the '+' token.
2293 } else if (Tok.is(AsmToken::Minus)) {
2294 Parser.Lex(); // Eat the '-' token.
2298 if (Parser.getTok().is(AsmToken::Identifier))
2299 Reg = tryParseRegister();
2302 return MatchOperand_NoMatch;
2303 Error(Parser.getTok().getLoc(), "register expected");
2304 return MatchOperand_ParseFail;
2306 SMLoc E = Parser.getTok().getLoc();
2308 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2309 unsigned ShiftImm = 0;
2310 if (Parser.getTok().is(AsmToken::Comma)) {
2311 Parser.Lex(); // Eat the ','.
2312 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2313 return MatchOperand_ParseFail;
2316 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2319 return MatchOperand_Success;
2322 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2323 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2324 // Check for a post-index addressing register operand. Specifically:
2325 // am3offset := '+' register
2332 // This method must return MatchOperand_NoMatch without consuming any tokens
2333 // in the case where there is no match, as other alternatives take other
2335 AsmToken Tok = Parser.getTok();
2336 SMLoc S = Tok.getLoc();
2338 // Do immediates first, as we always parse those if we have a '#'.
2339 if (Parser.getTok().is(AsmToken::Hash)) {
2340 Parser.Lex(); // Eat the '#'.
2341 // Explicitly look for a '-', as we need to encode negative zero
2343 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2344 const MCExpr *Offset;
2345 if (getParser().ParseExpression(Offset))
2346 return MatchOperand_ParseFail;
2347 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2349 Error(S, "constant expression expected");
2350 return MatchOperand_ParseFail;
2352 SMLoc E = Tok.getLoc();
2353 // Negative zero is encoded as the flag value INT32_MIN.
2354 int32_t Val = CE->getValue();
2355 if (isNegative && Val == 0)
2359 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2361 return MatchOperand_Success;
2365 bool haveEaten = false;
2368 if (Tok.is(AsmToken::Plus)) {
2369 Parser.Lex(); // Eat the '+' token.
2371 } else if (Tok.is(AsmToken::Minus)) {
2372 Parser.Lex(); // Eat the '-' token.
2376 if (Parser.getTok().is(AsmToken::Identifier))
2377 Reg = tryParseRegister();
2380 return MatchOperand_NoMatch;
2381 Error(Parser.getTok().getLoc(), "register expected");
2382 return MatchOperand_ParseFail;
2384 SMLoc E = Parser.getTok().getLoc();
2386 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2389 return MatchOperand_Success;
2392 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2393 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2394 /// when they refer multiple MIOperands inside a single one.
2396 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2397 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2398 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2400 // Create a writeback register dummy placeholder.
2401 Inst.addOperand(MCOperand::CreateImm(0));
2403 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2404 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2408 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2409 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2410 /// when they refer multiple MIOperands inside a single one.
2412 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2413 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2414 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2416 // Create a writeback register dummy placeholder.
2417 Inst.addOperand(MCOperand::CreateImm(0));
2419 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2420 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2425 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2426 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2427 /// when they refer multiple MIOperands inside a single one.
2429 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2430 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2431 // Create a writeback register dummy placeholder.
2432 Inst.addOperand(MCOperand::CreateImm(0));
2433 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2434 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2435 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2439 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2440 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2441 /// when they refer multiple MIOperands inside a single one.
2443 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2444 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2445 // Create a writeback register dummy placeholder.
2446 Inst.addOperand(MCOperand::CreateImm(0));
2447 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2448 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2449 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2453 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2454 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2455 /// when they refer multiple MIOperands inside a single one.
2457 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2458 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2459 // Create a writeback register dummy placeholder.
2460 Inst.addOperand(MCOperand::CreateImm(0));
2461 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2462 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2463 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2467 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2468 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2469 /// when they refer multiple MIOperands inside a single one.
2471 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2472 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2474 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2475 // Create a writeback register dummy placeholder.
2476 Inst.addOperand(MCOperand::CreateImm(0));
2478 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2480 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2482 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2486 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2487 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2488 /// when they refer multiple MIOperands inside a single one.
2490 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2491 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2493 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2494 // Create a writeback register dummy placeholder.
2495 Inst.addOperand(MCOperand::CreateImm(0));
2497 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2499 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2501 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2505 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2506 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2507 /// when they refer multiple MIOperands inside a single one.
2509 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2510 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2511 // Create a writeback register dummy placeholder.
2512 Inst.addOperand(MCOperand::CreateImm(0));
2514 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2516 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2518 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2520 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2524 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2525 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2526 /// when they refer multiple MIOperands inside a single one.
2528 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2529 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2530 // Create a writeback register dummy placeholder.
2531 Inst.addOperand(MCOperand::CreateImm(0));
2533 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2535 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2537 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2539 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2543 /// cvtLdrdPre - Convert parsed operands to MCInst.
2544 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2545 /// when they refer multiple MIOperands inside a single one.
2547 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2548 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2550 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2551 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2552 // Create a writeback register dummy placeholder.
2553 Inst.addOperand(MCOperand::CreateImm(0));
2555 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2557 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2561 /// cvtStrdPre - Convert parsed operands to MCInst.
2562 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2563 /// when they refer multiple MIOperands inside a single one.
2565 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2566 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2567 // Create a writeback register dummy placeholder.
2568 Inst.addOperand(MCOperand::CreateImm(0));
2570 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2571 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2573 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2575 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2579 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2580 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2581 /// when they refer multiple MIOperands inside a single one.
2583 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2584 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2585 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2586 // Create a writeback register dummy placeholder.
2587 Inst.addOperand(MCOperand::CreateImm(0));
2588 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2589 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2593 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2594 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2595 /// when they refer multiple MIOperands inside a single one.
2597 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2598 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2599 // The second source operand must be the same register as the destination
2601 if (Operands.size() == 6 &&
2602 (((ARMOperand*)Operands[3])->getReg() !=
2603 ((ARMOperand*)Operands[5])->getReg()) &&
2604 (((ARMOperand*)Operands[3])->getReg() !=
2605 ((ARMOperand*)Operands[4])->getReg())) {
2606 Error(Operands[3]->getStartLoc(),
2607 "destination register must match source register");
2610 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2611 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2612 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2613 // If we have a three-operand form, use that, else the second source operand
2614 // is just the destination operand again.
2615 if (Operands.size() == 6)
2616 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2618 Inst.addOperand(Inst.getOperand(0));
2619 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2624 /// Parse an ARM memory expression, return false if successful else return true
2625 /// or an error. The first token must be a '[' when called.
2627 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2629 assert(Parser.getTok().is(AsmToken::LBrac) &&
2630 "Token is not a Left Bracket");
2631 S = Parser.getTok().getLoc();
2632 Parser.Lex(); // Eat left bracket token.
2634 const AsmToken &BaseRegTok = Parser.getTok();
2635 int BaseRegNum = tryParseRegister();
2636 if (BaseRegNum == -1)
2637 return Error(BaseRegTok.getLoc(), "register expected");
2639 // The next token must either be a comma or a closing bracket.
2640 const AsmToken &Tok = Parser.getTok();
2641 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2642 return Error(Tok.getLoc(), "malformed memory operand");
2644 if (Tok.is(AsmToken::RBrac)) {
2646 Parser.Lex(); // Eat right bracket token.
2648 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2654 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2655 Parser.Lex(); // Eat the comma.
2657 // If we have a '#' it's an immediate offset, else assume it's a register
2659 if (Parser.getTok().is(AsmToken::Hash)) {
2660 Parser.Lex(); // Eat the '#'.
2661 E = Parser.getTok().getLoc();
2663 bool isNegative = getParser().getTok().is(AsmToken::Minus);
2664 const MCExpr *Offset;
2665 if (getParser().ParseExpression(Offset))
2668 // The expression has to be a constant. Memory references with relocations
2669 // don't come through here, as they use the <label> forms of the relevant
2671 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2673 return Error (E, "constant expression expected");
2675 // If the constant was #-0, represent it as INT32_MIN.
2676 int32_t Val = CE->getValue();
2677 if (isNegative && Val == 0)
2678 CE = MCConstantExpr::Create(INT32_MIN, getContext());
2680 // Now we should have the closing ']'
2681 E = Parser.getTok().getLoc();
2682 if (Parser.getTok().isNot(AsmToken::RBrac))
2683 return Error(E, "']' expected");
2684 Parser.Lex(); // Eat right bracket token.
2686 // Don't worry about range checking the value here. That's handled by
2687 // the is*() predicates.
2688 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2689 ARM_AM::no_shift, 0, false, S,E));
2691 // If there's a pre-indexing writeback marker, '!', just add it as a token
2693 if (Parser.getTok().is(AsmToken::Exclaim)) {
2694 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2695 Parser.Lex(); // Eat the '!'.
2701 // The register offset is optionally preceded by a '+' or '-'
2702 bool isNegative = false;
2703 if (Parser.getTok().is(AsmToken::Minus)) {
2705 Parser.Lex(); // Eat the '-'.
2706 } else if (Parser.getTok().is(AsmToken::Plus)) {
2708 Parser.Lex(); // Eat the '+'.
2711 E = Parser.getTok().getLoc();
2712 int OffsetRegNum = tryParseRegister();
2713 if (OffsetRegNum == -1)
2714 return Error(E, "register expected");
2716 // If there's a shift operator, handle it.
2717 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2718 unsigned ShiftImm = 0;
2719 if (Parser.getTok().is(AsmToken::Comma)) {
2720 Parser.Lex(); // Eat the ','.
2721 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2725 // Now we should have the closing ']'
2726 E = Parser.getTok().getLoc();
2727 if (Parser.getTok().isNot(AsmToken::RBrac))
2728 return Error(E, "']' expected");
2729 Parser.Lex(); // Eat right bracket token.
2731 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2732 ShiftType, ShiftImm, isNegative,
2735 // If there's a pre-indexing writeback marker, '!', just add it as a token
2737 if (Parser.getTok().is(AsmToken::Exclaim)) {
2738 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2739 Parser.Lex(); // Eat the '!'.
2745 /// parseMemRegOffsetShift - one of these two:
2746 /// ( lsl | lsr | asr | ror ) , # shift_amount
2748 /// return true if it parses a shift otherwise it returns false.
2749 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2751 SMLoc Loc = Parser.getTok().getLoc();
2752 const AsmToken &Tok = Parser.getTok();
2753 if (Tok.isNot(AsmToken::Identifier))
2755 StringRef ShiftName = Tok.getString();
2756 if (ShiftName == "lsl" || ShiftName == "LSL")
2758 else if (ShiftName == "lsr" || ShiftName == "LSR")
2760 else if (ShiftName == "asr" || ShiftName == "ASR")
2762 else if (ShiftName == "ror" || ShiftName == "ROR")
2764 else if (ShiftName == "rrx" || ShiftName == "RRX")
2767 return Error(Loc, "illegal shift operator");
2768 Parser.Lex(); // Eat shift type token.
2770 // rrx stands alone.
2772 if (St != ARM_AM::rrx) {
2773 Loc = Parser.getTok().getLoc();
2774 // A '#' and a shift amount.
2775 const AsmToken &HashTok = Parser.getTok();
2776 if (HashTok.isNot(AsmToken::Hash))
2777 return Error(HashTok.getLoc(), "'#' expected");
2778 Parser.Lex(); // Eat hash token.
2781 if (getParser().ParseExpression(Expr))
2783 // Range check the immediate.
2784 // lsl, ror: 0 <= imm <= 31
2785 // lsr, asr: 0 <= imm <= 32
2786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2788 return Error(Loc, "shift amount must be an immediate");
2789 int64_t Imm = CE->getValue();
2791 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2792 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2793 return Error(Loc, "immediate shift value out of range");
2800 /// Parse a arm instruction operand. For now this parses the operand regardless
2801 /// of the mnemonic.
2802 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2803 StringRef Mnemonic) {
2806 // Check if the current operand has a custom associated parser, if so, try to
2807 // custom parse the operand, or fallback to the general approach.
2808 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2809 if (ResTy == MatchOperand_Success)
2811 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2812 // there was a match, but an error occurred, in which case, just return that
2813 // the operand parsing failed.
2814 if (ResTy == MatchOperand_ParseFail)
2817 switch (getLexer().getKind()) {
2819 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2821 case AsmToken::Identifier: {
2822 if (!tryParseRegisterWithWriteBack(Operands))
2824 int Res = tryParseShiftRegister(Operands);
2825 if (Res == 0) // success
2827 else if (Res == -1) // irrecoverable error
2830 // Fall though for the Identifier case that is not a register or a
2833 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2834 case AsmToken::Dot: { // . as a branch target
2835 // This was not a register so parse other operands that start with an
2836 // identifier (like labels) as expressions and create them as immediates.
2837 const MCExpr *IdVal;
2838 S = Parser.getTok().getLoc();
2839 if (getParser().ParseExpression(IdVal))
2841 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2842 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2845 case AsmToken::LBrac:
2846 return parseMemory(Operands);
2847 case AsmToken::LCurly:
2848 return parseRegisterList(Operands);
2849 case AsmToken::Hash: {
2850 // #42 -> immediate.
2851 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2852 S = Parser.getTok().getLoc();
2854 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2855 const MCExpr *ImmVal;
2856 if (getParser().ParseExpression(ImmVal))
2858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
2860 Error(S, "constant expression expected");
2861 return MatchOperand_ParseFail;
2863 int32_t Val = CE->getValue();
2864 if (isNegative && Val == 0)
2865 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
2866 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2867 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2870 case AsmToken::Colon: {
2871 // ":lower16:" and ":upper16:" expression prefixes
2872 // FIXME: Check it's an expression prefix,
2873 // e.g. (FOO - :lower16:BAR) isn't legal.
2874 ARMMCExpr::VariantKind RefKind;
2875 if (parsePrefix(RefKind))
2878 const MCExpr *SubExprVal;
2879 if (getParser().ParseExpression(SubExprVal))
2882 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2884 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2885 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2891 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2892 // :lower16: and :upper16:.
2893 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2894 RefKind = ARMMCExpr::VK_ARM_None;
2896 // :lower16: and :upper16: modifiers
2897 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2898 Parser.Lex(); // Eat ':'
2900 if (getLexer().isNot(AsmToken::Identifier)) {
2901 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2905 StringRef IDVal = Parser.getTok().getIdentifier();
2906 if (IDVal == "lower16") {
2907 RefKind = ARMMCExpr::VK_ARM_LO16;
2908 } else if (IDVal == "upper16") {
2909 RefKind = ARMMCExpr::VK_ARM_HI16;
2911 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2916 if (getLexer().isNot(AsmToken::Colon)) {
2917 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2920 Parser.Lex(); // Eat the last ':'
2925 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2926 MCSymbolRefExpr::VariantKind Variant) {
2927 // Recurse over the given expression, rebuilding it to apply the given variant
2928 // to the leftmost symbol.
2929 if (Variant == MCSymbolRefExpr::VK_None)
2932 switch (E->getKind()) {
2933 case MCExpr::Target:
2934 llvm_unreachable("Can't handle target expr yet");
2935 case MCExpr::Constant:
2936 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2938 case MCExpr::SymbolRef: {
2939 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2941 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2944 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2948 llvm_unreachable("Can't handle unary expressions yet");
2950 case MCExpr::Binary: {
2951 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2952 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2953 const MCExpr *RHS = BE->getRHS();
2957 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2961 assert(0 && "Invalid expression kind!");
2965 /// \brief Given a mnemonic, split out possible predication code and carry
2966 /// setting letters to form a canonical mnemonic and flags.
2968 // FIXME: Would be nice to autogen this.
2969 // FIXME: This is a bit of a maze of special cases.
2970 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2971 unsigned &PredicationCode,
2973 unsigned &ProcessorIMod,
2974 StringRef &ITMask) {
2975 PredicationCode = ARMCC::AL;
2976 CarrySetting = false;
2979 // Ignore some mnemonics we know aren't predicated forms.
2981 // FIXME: Would be nice to autogen this.
2982 if ((Mnemonic == "movs" && isThumb()) ||
2983 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2984 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2985 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2986 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2987 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2988 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2989 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2992 // First, split out any predication code. Ignore mnemonics we know aren't
2993 // predicated but do have a carry-set and so weren't caught above.
2994 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2995 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2996 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
2997 Mnemonic != "sbcs" && Mnemonic != "rscs") {
2998 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2999 .Case("eq", ARMCC::EQ)
3000 .Case("ne", ARMCC::NE)
3001 .Case("hs", ARMCC::HS)
3002 .Case("cs", ARMCC::HS)
3003 .Case("lo", ARMCC::LO)
3004 .Case("cc", ARMCC::LO)
3005 .Case("mi", ARMCC::MI)
3006 .Case("pl", ARMCC::PL)
3007 .Case("vs", ARMCC::VS)
3008 .Case("vc", ARMCC::VC)
3009 .Case("hi", ARMCC::HI)
3010 .Case("ls", ARMCC::LS)
3011 .Case("ge", ARMCC::GE)
3012 .Case("lt", ARMCC::LT)
3013 .Case("gt", ARMCC::GT)
3014 .Case("le", ARMCC::LE)
3015 .Case("al", ARMCC::AL)
3018 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3019 PredicationCode = CC;
3023 // Next, determine if we have a carry setting bit. We explicitly ignore all
3024 // the instructions we know end in 's'.
3025 if (Mnemonic.endswith("s") &&
3026 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3027 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3028 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3029 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3030 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3031 (Mnemonic == "movs" && isThumb()))) {
3032 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3033 CarrySetting = true;
3036 // The "cps" instruction can have a interrupt mode operand which is glued into
3037 // the mnemonic. Check if this is the case, split it and parse the imod op
3038 if (Mnemonic.startswith("cps")) {
3039 // Split out any imod code.
3041 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3042 .Case("ie", ARM_PROC::IE)
3043 .Case("id", ARM_PROC::ID)
3046 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3047 ProcessorIMod = IMod;
3051 // The "it" instruction has the condition mask on the end of the mnemonic.
3052 if (Mnemonic.startswith("it")) {
3053 ITMask = Mnemonic.slice(2, Mnemonic.size());
3054 Mnemonic = Mnemonic.slice(0, 2);
3060 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3061 /// inclusion of carry set or predication code operands.
3063 // FIXME: It would be nice to autogen this.
3065 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3066 bool &CanAcceptPredicationCode) {
3067 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3068 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3069 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
3070 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3071 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3072 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3073 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
3074 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "neg" ||
3075 (Mnemonic == "mov" && !isThumb())) {
3076 CanAcceptCarrySet = true;
3078 CanAcceptCarrySet = false;
3081 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3082 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3083 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3084 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3085 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3086 (Mnemonic == "clrex" && !isThumb()) ||
3087 (Mnemonic == "nop" && isThumbOne()) ||
3088 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3090 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3092 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
3093 CanAcceptPredicationCode = false;
3095 CanAcceptPredicationCode = true;
3099 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3100 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3101 CanAcceptPredicationCode = false;
3104 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3105 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3106 // FIXME: This is all horribly hacky. We really need a better way to deal
3107 // with optional operands like this in the matcher table.
3109 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3110 // another does not. Specifically, the MOVW instruction does not. So we
3111 // special case it here and remove the defaulted (non-setting) cc_out
3112 // operand if that's the instruction we're trying to match.
3114 // We do this as post-processing of the explicit operands rather than just
3115 // conditionally adding the cc_out in the first place because we need
3116 // to check the type of the parsed immediate operand.
3117 if (Mnemonic == "mov" && Operands.size() > 4 &&
3118 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3119 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3120 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3123 // Register-register 'add' for thumb does not have a cc_out operand
3124 // when there are only two register operands.
3125 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3126 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3127 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3128 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3130 // Register-register 'add' for thumb does not have a cc_out operand
3131 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3132 // have to check the immediate range here since Thumb2 has a variant
3133 // that can handle a different range and has a cc_out operand.
3134 if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
3135 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3136 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3137 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3138 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3139 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3140 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3142 // For Thumb2, add immediate does not have a cc_out operand for the
3143 // imm0_4096 variant. That's the least-preferred variant when
3144 // selecting via the generic "add" mnemonic, so to know that we
3145 // should remove the cc_out operand, we have to explicitly check that
3146 // it's not one of the other variants. Ugh.
3147 if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
3148 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3149 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3150 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3151 // Nest conditions rather than one big 'if' statement for readability.
3153 // If either register is a high reg, it's either one of the SP
3154 // variants (handled above) or a 32-bit encoding, so we just
3155 // check against T3.
3156 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3157 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3158 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3160 // If both registers are low, we're in an IT block, and the immediate is
3161 // in range, we should use encoding T1 instead, which has a cc_out.
3163 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3164 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3165 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3168 // Otherwise, we use encoding T4, which does not have a cc_out
3174 // Register-register 'add/sub' for thumb does not have a cc_out operand
3175 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3176 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3177 // right, this will result in better diagnostics (which operand is off)
3179 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3180 (Operands.size() == 5 || Operands.size() == 6) &&
3181 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3182 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3183 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3189 /// Parse an arm instruction mnemonic followed by its operands.
3190 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3191 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3192 // Create the leading tokens for the mnemonic, split by '.' characters.
3193 size_t Start = 0, Next = Name.find('.');
3194 StringRef Mnemonic = Name.slice(Start, Next);
3196 // Split out the predication code and carry setting flag from the mnemonic.
3197 unsigned PredicationCode;
3198 unsigned ProcessorIMod;
3201 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3202 ProcessorIMod, ITMask);
3204 // In Thumb1, only the branch (B) instruction can be predicated.
3205 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3206 Parser.EatToEndOfStatement();
3207 return Error(NameLoc, "conditional execution not supported in Thumb1");
3210 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3212 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3213 // is the mask as it will be for the IT encoding if the conditional
3214 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3215 // where the conditional bit0 is zero, the instruction post-processing
3216 // will adjust the mask accordingly.
3217 if (Mnemonic == "it") {
3218 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3219 if (ITMask.size() > 3) {
3220 Parser.EatToEndOfStatement();
3221 return Error(Loc, "too many conditions on IT instruction");
3224 for (unsigned i = ITMask.size(); i != 0; --i) {
3225 char pos = ITMask[i - 1];
3226 if (pos != 't' && pos != 'e') {
3227 Parser.EatToEndOfStatement();
3228 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3231 if (ITMask[i - 1] == 't')
3234 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3237 // FIXME: This is all a pretty gross hack. We should automatically handle
3238 // optional operands like this via tblgen.
3240 // Next, add the CCOut and ConditionCode operands, if needed.
3242 // For mnemonics which can ever incorporate a carry setting bit or predication
3243 // code, our matching model involves us always generating CCOut and
3244 // ConditionCode operands to match the mnemonic "as written" and then we let
3245 // the matcher deal with finding the right instruction or generating an
3246 // appropriate error.
3247 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3248 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3250 // If we had a carry-set on an instruction that can't do that, issue an
3252 if (!CanAcceptCarrySet && CarrySetting) {
3253 Parser.EatToEndOfStatement();
3254 return Error(NameLoc, "instruction '" + Mnemonic +
3255 "' can not set flags, but 's' suffix specified");
3257 // If we had a predication code on an instruction that can't do that, issue an
3259 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3260 Parser.EatToEndOfStatement();
3261 return Error(NameLoc, "instruction '" + Mnemonic +
3262 "' is not predicable, but condition code specified");
3265 // Add the carry setting operand, if necessary.
3266 if (CanAcceptCarrySet) {
3267 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3268 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3272 // Add the predication code operand, if necessary.
3273 if (CanAcceptPredicationCode) {
3274 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3276 Operands.push_back(ARMOperand::CreateCondCode(
3277 ARMCC::CondCodes(PredicationCode), Loc));
3280 // Add the processor imod operand, if necessary.
3281 if (ProcessorIMod) {
3282 Operands.push_back(ARMOperand::CreateImm(
3283 MCConstantExpr::Create(ProcessorIMod, getContext()),
3287 // Add the remaining tokens in the mnemonic.
3288 while (Next != StringRef::npos) {
3290 Next = Name.find('.', Start + 1);
3291 StringRef ExtraToken = Name.slice(Start, Next);
3293 // For now, we're only parsing Thumb1 (for the most part), so
3294 // just ignore ".n" qualifiers. We'll use them to restrict
3295 // matching when we do Thumb2.
3296 if (ExtraToken != ".n") {
3297 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3298 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3302 // Read the remaining operands.
3303 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3304 // Read the first operand.
3305 if (parseOperand(Operands, Mnemonic)) {
3306 Parser.EatToEndOfStatement();
3310 while (getLexer().is(AsmToken::Comma)) {
3311 Parser.Lex(); // Eat the comma.
3313 // Parse and remember the operand.
3314 if (parseOperand(Operands, Mnemonic)) {
3315 Parser.EatToEndOfStatement();
3321 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3322 Parser.EatToEndOfStatement();
3323 return TokError("unexpected token in argument list");
3326 Parser.Lex(); // Consume the EndOfStatement
3328 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3329 // do and don't have a cc_out optional-def operand. With some spot-checks
3330 // of the operand list, we can figure out which variant we're trying to
3331 // parse and adjust accordingly before actually matching. We shouldn't ever
3332 // try to remove a cc_out operand that was explicitly set on the the
3333 // mnemonic, of course (CarrySetting == true). Reason number #317 the
3334 // table driven matcher doesn't fit well with the ARM instruction set.
3335 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3336 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3337 Operands.erase(Operands.begin() + 1);
3341 // ARM mode 'blx' need special handling, as the register operand version
3342 // is predicable, but the label operand version is not. So, we can't rely
3343 // on the Mnemonic based checking to correctly figure out when to put
3344 // a CondCode operand in the list. If we're trying to match the label
3345 // version, remove the CondCode operand here.
3346 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3347 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3348 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3349 Operands.erase(Operands.begin() + 1);
3353 // The vector-compare-to-zero instructions have a literal token "#0" at
3354 // the end that comes to here as an immediate operand. Convert it to a
3355 // token to play nicely with the matcher.
3356 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3357 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3358 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3359 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3360 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3361 if (CE && CE->getValue() == 0) {
3362 Operands.erase(Operands.begin() + 5);
3363 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3367 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3368 // end. Convert it to a token here.
3369 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3370 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3371 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3372 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3373 if (CE && CE->getValue() == 0) {
3374 Operands.erase(Operands.begin() + 5);
3375 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3383 // Validate context-sensitive operand constraints.
3385 // return 'true' if register list contains non-low GPR registers,
3386 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3387 // 'containsReg' to true.
3388 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3389 unsigned HiReg, bool &containsReg) {
3390 containsReg = false;
3391 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3392 unsigned OpReg = Inst.getOperand(i).getReg();
3395 // Anything other than a low register isn't legal here.
3396 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3402 // Check if the specified regisgter is in the register list of the inst,
3403 // starting at the indicated operand number.
3404 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3405 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3406 unsigned OpReg = Inst.getOperand(i).getReg();
3413 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3414 // the ARMInsts array) instead. Getting that here requires awkward
3415 // API changes, though. Better way?
3417 extern MCInstrDesc ARMInsts[];
3419 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3420 return ARMInsts[Opcode];
3423 // FIXME: We would really like to be able to tablegen'erate this.
3425 validateInstruction(MCInst &Inst,
3426 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3427 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3428 SMLoc Loc = Operands[0]->getStartLoc();
3429 // Check the IT block state first.
3432 if (ITState.FirstCond)
3433 ITState.FirstCond = false;
3435 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3436 // The instruction must be predicable.
3437 if (!MCID.isPredicable())
3438 return Error(Loc, "instructions in IT block must be predicable");
3439 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3440 unsigned ITCond = bit ? ITState.Cond :
3441 ARMCC::getOppositeCondition(ITState.Cond);
3442 if (Cond != ITCond) {
3443 // Find the condition code Operand to get its SMLoc information.
3445 for (unsigned i = 1; i < Operands.size(); ++i)
3446 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3447 CondLoc = Operands[i]->getStartLoc();
3448 return Error(CondLoc, "incorrect condition in IT block; got '" +
3449 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3450 "', but expected '" +
3451 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3453 // Check for non-'al' condition codes outside of the IT block.
3454 } else if (isThumbTwo() && MCID.isPredicable() &&
3455 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3456 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
3457 Inst.getOpcode() != ARM::t2Bcc)
3458 return Error(Loc, "predicated instructions must be in IT block");
3460 switch (Inst.getOpcode()) {
3463 case ARM::LDRD_POST:
3465 // Rt2 must be Rt + 1.
3466 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3467 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3469 return Error(Operands[3]->getStartLoc(),
3470 "destination operands must be sequential");
3474 // Rt2 must be Rt + 1.
3475 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3476 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3478 return Error(Operands[3]->getStartLoc(),
3479 "source operands must be sequential");
3483 case ARM::STRD_POST:
3485 // Rt2 must be Rt + 1.
3486 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3487 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3489 return Error(Operands[3]->getStartLoc(),
3490 "source operands must be sequential");
3495 // width must be in range [1, 32-lsb]
3496 unsigned lsb = Inst.getOperand(2).getImm();
3497 unsigned widthm1 = Inst.getOperand(3).getImm();
3498 if (widthm1 >= 32 - lsb)
3499 return Error(Operands[5]->getStartLoc(),
3500 "bitfield width must be in range [1,32-lsb]");
3504 // If we're parsing Thumb2, the .w variant is available and handles
3505 // most cases that are normally illegal for a Thumb1 LDM
3506 // instruction. We'll make the transformation in processInstruction()
3509 // Thumb LDM instructions are writeback iff the base register is not
3510 // in the register list.
3511 unsigned Rn = Inst.getOperand(0).getReg();
3512 bool hasWritebackToken =
3513 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3514 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3515 bool listContainsBase;
3516 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3517 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3518 "registers must be in range r0-r7");
3519 // If we should have writeback, then there should be a '!' token.
3520 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3521 return Error(Operands[2]->getStartLoc(),
3522 "writeback operator '!' expected");
3523 // If we should not have writeback, there must not be a '!'. This is
3524 // true even for the 32-bit wide encodings.
3525 if (listContainsBase && hasWritebackToken)
3526 return Error(Operands[3]->getStartLoc(),
3527 "writeback operator '!' not allowed when base register "
3528 "in register list");
3532 case ARM::t2LDMIA_UPD: {
3533 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3534 return Error(Operands[4]->getStartLoc(),
3535 "writeback operator '!' not allowed when base register "
3536 "in register list");
3540 bool listContainsBase;
3541 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3542 return Error(Operands[2]->getStartLoc(),
3543 "registers must be in range r0-r7 or pc");
3547 bool listContainsBase;
3548 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3549 return Error(Operands[2]->getStartLoc(),
3550 "registers must be in range r0-r7 or lr");
3553 case ARM::tSTMIA_UPD: {
3554 bool listContainsBase;
3555 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase))
3556 return Error(Operands[4]->getStartLoc(),
3557 "registers must be in range r0-r7");
3566 processInstruction(MCInst &Inst,
3567 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3568 switch (Inst.getOpcode()) {
3569 case ARM::LDMIA_UPD:
3570 // If this is a load of a single register via a 'pop', then we should use
3571 // a post-indexed LDR instruction instead, per the ARM ARM.
3572 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3573 Inst.getNumOperands() == 5) {
3575 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3576 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3577 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3578 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3579 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3580 TmpInst.addOperand(MCOperand::CreateImm(4));
3581 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3582 TmpInst.addOperand(Inst.getOperand(3));
3586 case ARM::STMDB_UPD:
3587 // If this is a store of a single register via a 'push', then we should use
3588 // a pre-indexed STR instruction instead, per the ARM ARM.
3589 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3590 Inst.getNumOperands() == 5) {
3592 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3593 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3594 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3595 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3596 TmpInst.addOperand(MCOperand::CreateImm(-4));
3597 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3598 TmpInst.addOperand(Inst.getOperand(3));
3603 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3604 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3605 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3606 // to encoding T1 if <Rd> is omitted."
3607 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3608 Inst.setOpcode(ARM::tADDi3);
3611 // If the conditional is AL or we're in an IT block, we really want t2B.
3612 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3613 Inst.setOpcode(ARM::t2B);
3616 // If the conditional is AL, we really want tB.
3617 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3618 Inst.setOpcode(ARM::tB);
3621 // If the register list contains any high registers, or if the writeback
3622 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3623 // instead if we're in Thumb2. Otherwise, this should have generated
3624 // an error in validateInstruction().
3625 unsigned Rn = Inst.getOperand(0).getReg();
3626 bool hasWritebackToken =
3627 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3628 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3629 bool listContainsBase;
3630 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3631 (!listContainsBase && !hasWritebackToken) ||
3632 (listContainsBase && hasWritebackToken)) {
3633 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3634 assert (isThumbTwo());
3635 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3636 // If we're switching to the updating version, we need to insert
3637 // the writeback tied operand.
3638 if (hasWritebackToken)
3639 Inst.insert(Inst.begin(),
3640 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3645 // The mask bits for all but the first condition are represented as
3646 // the low bit of the condition code value implies 't'. We currently
3647 // always have 1 implies 't', so XOR toggle the bits if the low bit
3648 // of the condition code is zero. The encoding also expects the low
3649 // bit of the condition to be encoded as bit 4 of the mask operand,
3650 // so mask that in if needed
3651 MCOperand &MO = Inst.getOperand(1);
3652 unsigned Mask = MO.getImm();
3653 unsigned OrigMask = Mask;
3654 unsigned TZ = CountTrailingZeros_32(Mask);
3655 if ((Inst.getOperand(0).getImm() & 1) == 0) {
3656 assert(Mask && TZ <= 3 && "illegal IT mask value!");
3657 for (unsigned i = 3; i != TZ; --i)
3663 // Set up the IT block state according to the IT instruction we just
3665 assert(!inITBlock() && "nested IT blocks?!");
3666 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3667 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3668 ITState.CurPosition = 0;
3669 ITState.FirstCond = true;
3675 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3676 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3677 // suffix depending on whether they're in an IT block or not.
3678 unsigned Opc = Inst.getOpcode();
3679 MCInstrDesc &MCID = getInstDesc(Opc);
3680 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3681 assert(MCID.hasOptionalDef() &&
3682 "optionally flag setting instruction missing optional def operand");
3683 assert(MCID.NumOperands == Inst.getNumOperands() &&
3684 "operand count mismatch!");
3685 // Find the optional-def operand (cc_out).
3688 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3691 // If we're parsing Thumb1, reject it completely.
3692 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3693 return Match_MnemonicFail;
3694 // If we're parsing Thumb2, which form is legal depends on whether we're
3696 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3698 return Match_RequiresITBlock;
3699 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3701 return Match_RequiresNotITBlock;
3703 // Some high-register supporting Thumb1 encodings only allow both registers
3704 // to be from r0-r7 when in Thumb2.
3705 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3706 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3707 isARMLowRegister(Inst.getOperand(2).getReg()))
3708 return Match_RequiresThumb2;
3709 // Others only require ARMv6 or later.
3710 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3711 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3712 isARMLowRegister(Inst.getOperand(1).getReg()))
3713 return Match_RequiresV6;
3714 return Match_Success;
3718 MatchAndEmitInstruction(SMLoc IDLoc,
3719 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3723 unsigned MatchResult;
3724 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3725 switch (MatchResult) {
3728 // Context sensitive operand constraints aren't handled by the matcher,
3729 // so check them here.
3730 if (validateInstruction(Inst, Operands)) {
3731 // Still progress the IT block, otherwise one wrong condition causes
3732 // nasty cascading errors.
3733 forwardITPosition();
3737 // Some instructions need post-processing to, for example, tweak which
3738 // encoding is selected.
3739 processInstruction(Inst, Operands);
3741 // Only move forward at the very end so that everything in validate
3742 // and process gets a consistent answer about whether we're in an IT
3744 forwardITPosition();
3746 Out.EmitInstruction(Inst);
3748 case Match_MissingFeature:
3749 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3751 case Match_InvalidOperand: {
3752 SMLoc ErrorLoc = IDLoc;
3753 if (ErrorInfo != ~0U) {
3754 if (ErrorInfo >= Operands.size())
3755 return Error(IDLoc, "too few operands for instruction");
3757 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3758 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3761 return Error(ErrorLoc, "invalid operand for instruction");
3763 case Match_MnemonicFail:
3764 return Error(IDLoc, "invalid instruction");
3765 case Match_ConversionFail:
3766 // The converter function will have already emited a diagnostic.
3768 case Match_RequiresNotITBlock:
3769 return Error(IDLoc, "flag setting instruction only valid outside IT block");
3770 case Match_RequiresITBlock:
3771 return Error(IDLoc, "instruction only valid inside IT block");
3772 case Match_RequiresV6:
3773 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3774 case Match_RequiresThumb2:
3775 return Error(IDLoc, "instruction variant requires Thumb2");
3778 llvm_unreachable("Implement any new match types added!");
3782 /// parseDirective parses the arm specific directives
3783 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3784 StringRef IDVal = DirectiveID.getIdentifier();
3785 if (IDVal == ".word")
3786 return parseDirectiveWord(4, DirectiveID.getLoc());
3787 else if (IDVal == ".thumb")
3788 return parseDirectiveThumb(DirectiveID.getLoc());
3789 else if (IDVal == ".thumb_func")
3790 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3791 else if (IDVal == ".code")
3792 return parseDirectiveCode(DirectiveID.getLoc());
3793 else if (IDVal == ".syntax")
3794 return parseDirectiveSyntax(DirectiveID.getLoc());
3798 /// parseDirectiveWord
3799 /// ::= .word [ expression (, expression)* ]
3800 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3801 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3803 const MCExpr *Value;
3804 if (getParser().ParseExpression(Value))
3807 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3809 if (getLexer().is(AsmToken::EndOfStatement))
3812 // FIXME: Improve diagnostic.
3813 if (getLexer().isNot(AsmToken::Comma))
3814 return Error(L, "unexpected token in directive");
3823 /// parseDirectiveThumb
3825 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3826 if (getLexer().isNot(AsmToken::EndOfStatement))
3827 return Error(L, "unexpected token in directive");
3830 // TODO: set thumb mode
3831 // TODO: tell the MC streamer the mode
3832 // getParser().getStreamer().Emit???();
3836 /// parseDirectiveThumbFunc
3837 /// ::= .thumbfunc symbol_name
3838 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3839 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3840 bool isMachO = MAI.hasSubsectionsViaSymbols();
3843 // Darwin asm has function name after .thumb_func direction
3846 const AsmToken &Tok = Parser.getTok();
3847 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3848 return Error(L, "unexpected token in .thumb_func directive");
3849 Name = Tok.getString();
3850 Parser.Lex(); // Consume the identifier token.
3853 if (getLexer().isNot(AsmToken::EndOfStatement))
3854 return Error(L, "unexpected token in directive");
3857 // FIXME: assuming function name will be the line following .thumb_func
3859 Name = Parser.getTok().getString();
3862 // Mark symbol as a thumb symbol.
3863 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3864 getParser().getStreamer().EmitThumbFunc(Func);
3868 /// parseDirectiveSyntax
3869 /// ::= .syntax unified | divided
3870 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3871 const AsmToken &Tok = Parser.getTok();
3872 if (Tok.isNot(AsmToken::Identifier))
3873 return Error(L, "unexpected token in .syntax directive");
3874 StringRef Mode = Tok.getString();
3875 if (Mode == "unified" || Mode == "UNIFIED")
3877 else if (Mode == "divided" || Mode == "DIVIDED")
3878 return Error(L, "'.syntax divided' arm asssembly not supported");
3880 return Error(L, "unrecognized syntax mode in .syntax directive");
3882 if (getLexer().isNot(AsmToken::EndOfStatement))
3883 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3886 // TODO tell the MC streamer the mode
3887 // getParser().getStreamer().Emit???();
3891 /// parseDirectiveCode
3892 /// ::= .code 16 | 32
3893 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3894 const AsmToken &Tok = Parser.getTok();
3895 if (Tok.isNot(AsmToken::Integer))
3896 return Error(L, "unexpected token in .code directive");
3897 int64_t Val = Parser.getTok().getIntVal();
3903 return Error(L, "invalid operand to .code directive");
3905 if (getLexer().isNot(AsmToken::EndOfStatement))
3906 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3912 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3916 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3922 extern "C" void LLVMInitializeARMAsmLexer();
3924 /// Force static initialization.
3925 extern "C" void LLVMInitializeARMAsmParser() {
3926 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3927 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3928 LLVMInitializeARMAsmLexer();
3931 #define GET_REGISTER_MATCHER
3932 #define GET_MATCHER_IMPLEMENTATION
3933 #include "ARMGenAsmMatcher.inc"