1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMSubtarget.h"
12 #include "llvm/MC/MCParser/MCAsmLexer.h"
13 #include "llvm/MC/MCParser/MCAsmParser.h"
14 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
15 #include "llvm/MC/MCStreamer.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetRegistry.h"
19 #include "llvm/Target/TargetAsmParser.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/SourceMgr.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Twine.h"
32 // The shift types for register controlled shifts in arm memory addressing
41 class ARMAsmParser : public TargetAsmParser {
46 MCAsmParser &getParser() const { return Parser; }
48 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
50 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
52 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
54 bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
56 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
58 bool ParseMemory(OwningPtr<ARMOperand> &Op);
60 bool ParseMemoryOffsetReg(bool &Negative,
61 bool &OffsetRegShifted,
62 enum ShiftType &ShiftType,
63 const MCExpr *&ShiftAmount,
64 const MCExpr *&Offset,
69 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
71 bool ParseOperand(OwningPtr<ARMOperand> &Op);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
75 bool ParseDirectiveThumb(SMLoc L);
77 bool ParseDirectiveThumbFunc(SMLoc L);
79 bool ParseDirectiveCode(SMLoc L);
81 bool ParseDirectiveSyntax(SMLoc L);
83 bool MatchAndEmitInstruction(SMLoc IDLoc,
84 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 if (MatchInstructionImpl(Operands, Inst, ErrorInfo) == Match_Success) {
89 Out.EmitInstruction(Inst);
93 // FIXME: We should give nicer diagnostics about the exact failure.
94 Error(IDLoc, "unrecognized instruction");
98 /// @name Auto-generated Match Functions
101 #define GET_ASSEMBLER_HEADER
102 #include "ARMGenAsmMatcher.inc"
108 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
109 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {}
111 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
112 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 virtual bool ParseDirective(AsmToken DirectiveID);
117 /// ARMOperand - Instances of this class represent a parsed ARM machine
119 struct ARMOperand : public MCParsedAsmOperand {
131 SMLoc StartLoc, EndLoc;
135 ARMCC::CondCodes Val;
152 // This is for all forms of ARM address expressions
155 unsigned OffsetRegNum; // used when OffsetIsReg is true
156 const MCExpr *Offset; // used when OffsetIsReg is false
157 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
158 enum ShiftType ShiftType; // used when OffsetRegShifted is true
160 OffsetRegShifted : 1, // only used when OffsetIsReg is true
164 Negative : 1, // only used when OffsetIsReg is true
170 //ARMOperand(KindTy K, SMLoc S, SMLoc E)
171 // : Kind(K), StartLoc(S), EndLoc(E) {}
173 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
175 StartLoc = o.StartLoc;
196 /// getStartLoc - Get the location of the first token of this operand.
197 SMLoc getStartLoc() const { return StartLoc; }
198 /// getEndLoc - Get the location of the last token of this operand.
199 SMLoc getEndLoc() const { return EndLoc; }
201 ARMCC::CondCodes getCondCode() const {
202 assert(Kind == CondCode && "Invalid access!");
206 StringRef getToken() const {
207 assert(Kind == Token && "Invalid access!");
208 return StringRef(Tok.Data, Tok.Length);
211 unsigned getReg() const {
212 assert(Kind == Register && "Invalid access!");
216 const MCExpr *getImm() const {
217 assert(Kind == Immediate && "Invalid access!");
221 bool isCondCode() const { return Kind == CondCode; }
223 bool isImm() const { return Kind == Immediate; }
225 bool isReg() const { return Kind == Register; }
227 bool isToken() const {return Kind == Token; }
229 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
230 // Add as immediates when possible.
231 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
232 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
234 Inst.addOperand(MCOperand::CreateExpr(Expr));
237 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
238 assert(N == 2 && "Invalid number of operands!");
239 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
240 // FIXME: What belongs here?
241 Inst.addOperand(MCOperand::CreateReg(0));
244 void addRegOperands(MCInst &Inst, unsigned N) const {
245 assert(N == 1 && "Invalid number of operands!");
246 Inst.addOperand(MCOperand::CreateReg(getReg()));
249 void addImmOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 1 && "Invalid number of operands!");
251 addExpr(Inst, getImm());
254 virtual void dump(raw_ostream &OS) const;
256 static void CreateCondCode(OwningPtr<ARMOperand> &Op, ARMCC::CondCodes CC,
258 Op.reset(new ARMOperand);
265 static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
267 Op.reset(new ARMOperand);
269 Op->Tok.Data = Str.data();
270 Op->Tok.Length = Str.size();
275 static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
276 bool Writeback, SMLoc S, SMLoc E) {
277 Op.reset(new ARMOperand);
279 Op->Reg.RegNum = RegNum;
280 Op->Reg.Writeback = Writeback;
286 static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
288 Op.reset(new ARMOperand);
289 Op->Kind = Immediate;
296 static void CreateMem(OwningPtr<ARMOperand> &Op,
297 unsigned BaseRegNum, bool OffsetIsReg,
298 const MCExpr *Offset, unsigned OffsetRegNum,
299 bool OffsetRegShifted, enum ShiftType ShiftType,
300 const MCExpr *ShiftAmount, bool Preindexed,
301 bool Postindexed, bool Negative, bool Writeback,
303 Op.reset(new ARMOperand);
305 Op->Mem.BaseRegNum = BaseRegNum;
306 Op->Mem.OffsetIsReg = OffsetIsReg;
307 Op->Mem.Offset = Offset;
308 Op->Mem.OffsetRegNum = OffsetRegNum;
309 Op->Mem.OffsetRegShifted = OffsetRegShifted;
310 Op->Mem.ShiftType = ShiftType;
311 Op->Mem.ShiftAmount = ShiftAmount;
312 Op->Mem.Preindexed = Preindexed;
313 Op->Mem.Postindexed = Postindexed;
314 Op->Mem.Negative = Negative;
315 Op->Mem.Writeback = Writeback;
322 } // end anonymous namespace.
324 void ARMOperand::dump(raw_ostream &OS) const {
327 OS << ARMCondCodeToString(getCondCode());
336 OS << "<register " << getReg() << ">";
339 OS << "'" << getToken() << "'";
344 /// @name Auto-generated Match Functions
347 static unsigned MatchRegisterName(StringRef Name);
351 /// Try to parse a register name. The token must be an Identifier when called,
352 /// and if it is a register name a Reg operand is created, the token is eaten
353 /// and false is returned. Else true is returned and no token is eaten.
354 /// TODO this is likely to change to allow different register types and or to
355 /// parse for a specific register type.
356 bool ARMAsmParser::MaybeParseRegister
357 (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
359 const AsmToken &Tok = Parser.getTok();
360 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
362 // FIXME: Validate register for the current architecture; we have to do
363 // validation later, so maybe there is no need for this here.
366 RegNum = MatchRegisterName(Tok.getString());
372 Parser.Lex(); // Eat identifier token.
374 E = Parser.getTok().getLoc();
376 bool Writeback = false;
377 if (ParseWriteBack) {
378 const AsmToken &ExclaimTok = Parser.getTok();
379 if (ExclaimTok.is(AsmToken::Exclaim)) {
380 E = ExclaimTok.getLoc();
382 Parser.Lex(); // Eat exclaim token
386 ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
391 /// Parse a register list, return false if successful else return true or an
392 /// error. The first token must be a '{' when called.
393 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
395 assert(Parser.getTok().is(AsmToken::LCurly) &&
396 "Token is not an Left Curly Brace");
397 S = Parser.getTok().getLoc();
398 Parser.Lex(); // Eat left curly brace token.
400 const AsmToken &RegTok = Parser.getTok();
401 SMLoc RegLoc = RegTok.getLoc();
402 if (RegTok.isNot(AsmToken::Identifier))
403 return Error(RegLoc, "register expected");
404 int RegNum = MatchRegisterName(RegTok.getString());
406 return Error(RegLoc, "register expected");
407 Parser.Lex(); // Eat identifier token.
408 unsigned RegList = 1 << RegNum;
410 int HighRegNum = RegNum;
411 // TODO ranges like "{Rn-Rm}"
412 while (Parser.getTok().is(AsmToken::Comma)) {
413 Parser.Lex(); // Eat comma token.
415 const AsmToken &RegTok = Parser.getTok();
416 SMLoc RegLoc = RegTok.getLoc();
417 if (RegTok.isNot(AsmToken::Identifier))
418 return Error(RegLoc, "register expected");
419 int RegNum = MatchRegisterName(RegTok.getString());
421 return Error(RegLoc, "register expected");
423 if (RegList & (1 << RegNum))
424 Warning(RegLoc, "register duplicated in register list");
425 else if (RegNum <= HighRegNum)
426 Warning(RegLoc, "register not in ascending order in register list");
427 RegList |= 1 << RegNum;
430 Parser.Lex(); // Eat identifier token.
432 const AsmToken &RCurlyTok = Parser.getTok();
433 if (RCurlyTok.isNot(AsmToken::RCurly))
434 return Error(RCurlyTok.getLoc(), "'}' expected");
435 E = RCurlyTok.getLoc();
436 Parser.Lex(); // Eat left curly brace token.
441 /// Parse an arm memory expression, return false if successful else return true
442 /// or an error. The first token must be a '[' when called.
443 /// TODO Only preindexing and postindexing addressing are started, unindexed
444 /// with option, etc are still to do.
445 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
447 assert(Parser.getTok().is(AsmToken::LBrac) &&
448 "Token is not an Left Bracket");
449 S = Parser.getTok().getLoc();
450 Parser.Lex(); // Eat left bracket token.
452 const AsmToken &BaseRegTok = Parser.getTok();
453 if (BaseRegTok.isNot(AsmToken::Identifier))
454 return Error(BaseRegTok.getLoc(), "register expected");
455 if (MaybeParseRegister(Op, false))
456 return Error(BaseRegTok.getLoc(), "register expected");
457 int BaseRegNum = Op->getReg();
459 bool Preindexed = false;
460 bool Postindexed = false;
461 bool OffsetIsReg = false;
462 bool Negative = false;
463 bool Writeback = false;
465 // First look for preindexed address forms, that is after the "[Rn" we now
466 // have to see if the next token is a comma.
467 const AsmToken &Tok = Parser.getTok();
468 if (Tok.is(AsmToken::Comma)) {
470 Parser.Lex(); // Eat comma token.
472 bool OffsetRegShifted;
473 enum ShiftType ShiftType;
474 const MCExpr *ShiftAmount;
475 const MCExpr *Offset;
476 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
477 Offset, OffsetIsReg, OffsetRegNum, E))
479 const AsmToken &RBracTok = Parser.getTok();
480 if (RBracTok.isNot(AsmToken::RBrac))
481 return Error(RBracTok.getLoc(), "']' expected");
482 E = RBracTok.getLoc();
483 Parser.Lex(); // Eat right bracket token.
485 const AsmToken &ExclaimTok = Parser.getTok();
486 if (ExclaimTok.is(AsmToken::Exclaim)) {
487 E = ExclaimTok.getLoc();
489 Parser.Lex(); // Eat exclaim token
491 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
492 OffsetRegShifted, ShiftType, ShiftAmount,
493 Preindexed, Postindexed, Negative, Writeback, S, E);
496 // The "[Rn" we have so far was not followed by a comma.
497 else if (Tok.is(AsmToken::RBrac)) {
498 // This is a post indexing addressing forms, that is a ']' follows after
503 Parser.Lex(); // Eat right bracket token.
505 int OffsetRegNum = 0;
506 bool OffsetRegShifted = false;
507 enum ShiftType ShiftType;
508 const MCExpr *ShiftAmount;
509 const MCExpr *Offset;
511 const AsmToken &NextTok = Parser.getTok();
512 if (NextTok.isNot(AsmToken::EndOfStatement)) {
513 if (NextTok.isNot(AsmToken::Comma))
514 return Error(NextTok.getLoc(), "',' expected");
515 Parser.Lex(); // Eat comma token.
516 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
517 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
522 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
523 OffsetRegShifted, ShiftType, ShiftAmount,
524 Preindexed, Postindexed, Negative, Writeback, S, E);
531 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
532 /// we will parse the following (were +/- means that a plus or minus is
537 /// we return false on success or an error otherwise.
538 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
539 bool &OffsetRegShifted,
540 enum ShiftType &ShiftType,
541 const MCExpr *&ShiftAmount,
542 const MCExpr *&Offset,
546 OwningPtr<ARMOperand> Op;
548 OffsetRegShifted = false;
551 const AsmToken &NextTok = Parser.getTok();
552 E = NextTok.getLoc();
553 if (NextTok.is(AsmToken::Plus))
554 Parser.Lex(); // Eat plus token.
555 else if (NextTok.is(AsmToken::Minus)) {
557 Parser.Lex(); // Eat minus token
559 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
560 const AsmToken &OffsetRegTok = Parser.getTok();
561 if (OffsetRegTok.is(AsmToken::Identifier)) {
562 OffsetIsReg = !MaybeParseRegister(Op, false);
565 OffsetRegNum = Op->getReg();
568 // If we parsed a register as the offset then their can be a shift after that
569 if (OffsetRegNum != -1) {
570 // Look for a comma then a shift
571 const AsmToken &Tok = Parser.getTok();
572 if (Tok.is(AsmToken::Comma)) {
573 Parser.Lex(); // Eat comma token.
575 const AsmToken &Tok = Parser.getTok();
576 if (ParseShift(ShiftType, ShiftAmount, E))
577 return Error(Tok.getLoc(), "shift expected");
578 OffsetRegShifted = true;
581 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
582 // Look for #offset following the "[Rn," or "[Rn],"
583 const AsmToken &HashTok = Parser.getTok();
584 if (HashTok.isNot(AsmToken::Hash))
585 return Error(HashTok.getLoc(), "'#' expected");
587 Parser.Lex(); // Eat hash token.
589 if (getParser().ParseExpression(Offset))
591 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
596 /// ParseShift as one of these two:
597 /// ( lsl | lsr | asr | ror ) , # shift_amount
599 /// and returns true if it parses a shift otherwise it returns false.
600 bool ARMAsmParser::ParseShift(ShiftType &St,
601 const MCExpr *&ShiftAmount,
603 const AsmToken &Tok = Parser.getTok();
604 if (Tok.isNot(AsmToken::Identifier))
606 StringRef ShiftName = Tok.getString();
607 if (ShiftName == "lsl" || ShiftName == "LSL")
609 else if (ShiftName == "lsr" || ShiftName == "LSR")
611 else if (ShiftName == "asr" || ShiftName == "ASR")
613 else if (ShiftName == "ror" || ShiftName == "ROR")
615 else if (ShiftName == "rrx" || ShiftName == "RRX")
619 Parser.Lex(); // Eat shift type token.
625 // Otherwise, there must be a '#' and a shift amount.
626 const AsmToken &HashTok = Parser.getTok();
627 if (HashTok.isNot(AsmToken::Hash))
628 return Error(HashTok.getLoc(), "'#' expected");
629 Parser.Lex(); // Eat hash token.
631 if (getParser().ParseExpression(ShiftAmount))
637 /// Parse a arm instruction operand. For now this parses the operand regardless
639 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
642 switch (getLexer().getKind()) {
643 case AsmToken::Identifier:
644 if (!MaybeParseRegister(Op, true))
646 // This was not a register so parse other operands that start with an
647 // identifier (like labels) as expressions and create them as immediates.
649 S = Parser.getTok().getLoc();
650 if (getParser().ParseExpression(IdVal))
652 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
653 ARMOperand::CreateImm(Op, IdVal, S, E);
655 case AsmToken::LBrac:
656 return ParseMemory(Op);
657 case AsmToken::LCurly:
658 return ParseRegisterList(Op);
661 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
662 S = Parser.getTok().getLoc();
664 const MCExpr *ImmVal;
665 if (getParser().ParseExpression(ImmVal))
667 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
668 ARMOperand::CreateImm(Op, ImmVal, S, E);
671 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
675 /// Parse an arm instruction mnemonic followed by its operands.
676 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
677 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
678 OwningPtr<ARMOperand> Op;
680 // Create the leading tokens for the mnemonic, split by '.' characters.
681 size_t Start = 0, Next = Name.find('.');
682 StringRef Head = Name.slice(Start, Next);
684 // Determine the predicate, if any.
686 // FIXME: We need a way to check whether a prefix supports predication,
687 // otherwise we will end up with an ambiguity for instructions that happen to
688 // end with a predicate name.
689 unsigned CC = StringSwitch<unsigned>(Head.substr(Head.size()-2))
690 .Case("eq", ARMCC::EQ)
691 .Case("ne", ARMCC::NE)
692 .Case("hs", ARMCC::HS)
693 .Case("lo", ARMCC::LO)
694 .Case("mi", ARMCC::MI)
695 .Case("pl", ARMCC::PL)
696 .Case("vs", ARMCC::VS)
697 .Case("vc", ARMCC::VC)
698 .Case("hi", ARMCC::HI)
699 .Case("ls", ARMCC::LS)
700 .Case("ge", ARMCC::GE)
701 .Case("lt", ARMCC::LT)
702 .Case("gt", ARMCC::GT)
703 .Case("le", ARMCC::LE)
704 .Case("al", ARMCC::AL)
707 Head = Head.slice(0, Head.size() - 2);
711 ARMOperand::CreateToken(Op, Head, NameLoc);
712 Operands.push_back(Op.take());
714 ARMOperand::CreateCondCode(Op, ARMCC::CondCodes(CC), NameLoc);
715 Operands.push_back(Op.take());
717 // Add the remaining tokens in the mnemonic.
718 while (Next != StringRef::npos) {
720 Next = Name.find('.', Start + 1);
721 Head = Name.slice(Start, Next);
723 ARMOperand::CreateToken(Op, Head, NameLoc);
724 Operands.push_back(Op.take());
727 // Read the remaining operands.
728 if (getLexer().isNot(AsmToken::EndOfStatement)) {
729 // Read the first operand.
730 OwningPtr<ARMOperand> Op;
731 if (ParseOperand(Op)) {
732 Parser.EatToEndOfStatement();
735 Operands.push_back(Op.take());
737 while (getLexer().is(AsmToken::Comma)) {
738 Parser.Lex(); // Eat the comma.
740 // Parse and remember the operand.
741 if (ParseOperand(Op)) {
742 Parser.EatToEndOfStatement();
745 Operands.push_back(Op.take());
749 if (getLexer().isNot(AsmToken::EndOfStatement)) {
750 Parser.EatToEndOfStatement();
751 return TokError("unexpected token in argument list");
753 Parser.Lex(); // Consume the EndOfStatement
757 /// ParseDirective parses the arm specific directives
758 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
759 StringRef IDVal = DirectiveID.getIdentifier();
760 if (IDVal == ".word")
761 return ParseDirectiveWord(4, DirectiveID.getLoc());
762 else if (IDVal == ".thumb")
763 return ParseDirectiveThumb(DirectiveID.getLoc());
764 else if (IDVal == ".thumb_func")
765 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
766 else if (IDVal == ".code")
767 return ParseDirectiveCode(DirectiveID.getLoc());
768 else if (IDVal == ".syntax")
769 return ParseDirectiveSyntax(DirectiveID.getLoc());
773 /// ParseDirectiveWord
774 /// ::= .word [ expression (, expression)* ]
775 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
776 if (getLexer().isNot(AsmToken::EndOfStatement)) {
779 if (getParser().ParseExpression(Value))
782 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
784 if (getLexer().is(AsmToken::EndOfStatement))
787 // FIXME: Improve diagnostic.
788 if (getLexer().isNot(AsmToken::Comma))
789 return Error(L, "unexpected token in directive");
798 /// ParseDirectiveThumb
800 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
801 if (getLexer().isNot(AsmToken::EndOfStatement))
802 return Error(L, "unexpected token in directive");
805 // TODO: set thumb mode
806 // TODO: tell the MC streamer the mode
807 // getParser().getStreamer().Emit???();
811 /// ParseDirectiveThumbFunc
812 /// ::= .thumbfunc symbol_name
813 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
814 const AsmToken &Tok = Parser.getTok();
815 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
816 return Error(L, "unexpected token in .syntax directive");
817 StringRef ATTRIBUTE_UNUSED SymbolName = Parser.getTok().getIdentifier();
818 Parser.Lex(); // Consume the identifier token.
820 if (getLexer().isNot(AsmToken::EndOfStatement))
821 return Error(L, "unexpected token in directive");
824 // TODO: mark symbol as a thumb symbol
825 // getParser().getStreamer().Emit???();
829 /// ParseDirectiveSyntax
830 /// ::= .syntax unified | divided
831 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
832 const AsmToken &Tok = Parser.getTok();
833 if (Tok.isNot(AsmToken::Identifier))
834 return Error(L, "unexpected token in .syntax directive");
835 StringRef Mode = Tok.getString();
836 if (Mode == "unified" || Mode == "UNIFIED")
838 else if (Mode == "divided" || Mode == "DIVIDED")
841 return Error(L, "unrecognized syntax mode in .syntax directive");
843 if (getLexer().isNot(AsmToken::EndOfStatement))
844 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
847 // TODO tell the MC streamer the mode
848 // getParser().getStreamer().Emit???();
852 /// ParseDirectiveCode
853 /// ::= .code 16 | 32
854 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
855 const AsmToken &Tok = Parser.getTok();
856 if (Tok.isNot(AsmToken::Integer))
857 return Error(L, "unexpected token in .code directive");
858 int64_t Val = Parser.getTok().getIntVal();
864 return Error(L, "invalid operand to .code directive");
866 if (getLexer().isNot(AsmToken::EndOfStatement))
867 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
870 // TODO tell the MC streamer the mode
871 // getParser().getStreamer().Emit???();
875 extern "C" void LLVMInitializeARMAsmLexer();
877 /// Force static initialization.
878 extern "C" void LLVMInitializeARMAsmParser() {
879 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
880 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
881 LLVMInitializeARMAsmLexer();
884 #define GET_REGISTER_MATCHER
885 #define GET_MATCHER_IMPLEMENTATION
886 #include "ARMGenAsmMatcher.inc"