1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public MCTargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int tryParseRegister();
51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
56 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
57 const MCExpr *applyPrefixToExpr(const MCExpr *E,
58 MCSymbolRefExpr::VariantKind Variant);
61 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
62 unsigned &ShiftAmount);
63 bool parseDirectiveWord(unsigned Size, SMLoc L);
64 bool parseDirectiveThumb(SMLoc L);
65 bool parseDirectiveThumbFunc(SMLoc L);
66 bool parseDirectiveCode(SMLoc L);
67 bool parseDirectiveSyntax(SMLoc L);
69 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
70 bool &CarrySetting, unsigned &ProcessorIMod);
71 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
72 bool &CanAcceptPredicationCode);
74 bool isThumb() const {
75 // FIXME: Can tablegen auto-generate this?
76 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
78 bool isThumbOne() const {
79 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
81 bool isThumbTwo() const {
82 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
84 bool hasV6Ops() const {
85 return STI.getFeatureBits() & ARM::HasV6Ops;
88 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
89 setAvailableFeatures(FB);
92 /// @name Auto-generated Match Functions
95 #define GET_ASSEMBLER_HEADER
96 #include "ARMGenAsmMatcher.inc"
100 OperandMatchResultTy parseCoprocNumOperand(
101 SmallVectorImpl<MCParsedAsmOperand*>&);
102 OperandMatchResultTy parseCoprocRegOperand(
103 SmallVectorImpl<MCParsedAsmOperand*>&);
104 OperandMatchResultTy parseMemBarrierOptOperand(
105 SmallVectorImpl<MCParsedAsmOperand*>&);
106 OperandMatchResultTy parseProcIFlagsOperand(
107 SmallVectorImpl<MCParsedAsmOperand*>&);
108 OperandMatchResultTy parseMSRMaskOperand(
109 SmallVectorImpl<MCParsedAsmOperand*>&);
110 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
111 StringRef Op, int Low, int High);
112 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
113 return parsePKHImm(O, "lsl", 0, 31);
115 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
116 return parsePKHImm(O, "asr", 1, 32);
118 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
119 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
120 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
122 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
123 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
125 // Asm Match Converter Methods
126 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
127 const SmallVectorImpl<MCParsedAsmOperand*> &);
128 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
129 const SmallVectorImpl<MCParsedAsmOperand*> &);
130 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
131 const SmallVectorImpl<MCParsedAsmOperand*> &);
132 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
133 const SmallVectorImpl<MCParsedAsmOperand*> &);
134 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
135 const SmallVectorImpl<MCParsedAsmOperand*> &);
136 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
137 const SmallVectorImpl<MCParsedAsmOperand*> &);
138 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
139 const SmallVectorImpl<MCParsedAsmOperand*> &);
140 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
141 const SmallVectorImpl<MCParsedAsmOperand*> &);
142 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
143 const SmallVectorImpl<MCParsedAsmOperand*> &);
144 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
145 const SmallVectorImpl<MCParsedAsmOperand*> &);
146 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
147 const SmallVectorImpl<MCParsedAsmOperand*> &);
149 bool validateInstruction(MCInst &Inst,
150 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
151 void processInstruction(MCInst &Inst,
152 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
153 bool shouldOmitCCOutOperand(StringRef Mnemonic,
154 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
157 enum ARMMatchResultTy {
158 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
163 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
164 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
165 MCAsmParserExtension::Initialize(_Parser);
167 // Initialize the set of available features.
168 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
171 // Implementation of the MCTargetAsmParser interface:
172 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
173 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
174 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
175 bool ParseDirective(AsmToken DirectiveID);
177 unsigned checkTargetMatchPredicate(MCInst &Inst);
179 bool MatchAndEmitInstruction(SMLoc IDLoc,
180 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
183 } // end anonymous namespace
187 /// ARMOperand - Instances of this class represent a parsed ARM machine
189 class ARMOperand : public MCParsedAsmOperand {
213 SMLoc StartLoc, EndLoc;
214 SmallVector<unsigned, 8> Registers;
218 ARMCC::CondCodes Val;
230 ARM_PROC::IFlags Val;
250 /// Combined record for all forms of ARM address expressions.
253 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
255 const MCConstantExpr *OffsetImm; // Offset immediate value
256 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
257 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
258 unsigned ShiftImm; // shift for OffsetReg.
259 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
265 ARM_AM::ShiftOpc ShiftTy;
274 ARM_AM::ShiftOpc ShiftTy;
280 ARM_AM::ShiftOpc ShiftTy;
293 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
295 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
297 StartLoc = o.StartLoc;
311 case DPRRegisterList:
312 case SPRRegisterList:
313 Registers = o.Registers;
328 case PostIndexRegister:
329 PostIdxReg = o.PostIdxReg;
337 case ShifterImmediate:
338 ShifterImm = o.ShifterImm;
340 case ShiftedRegister:
341 RegShiftedReg = o.RegShiftedReg;
343 case ShiftedImmediate:
344 RegShiftedImm = o.RegShiftedImm;
346 case RotateImmediate:
349 case BitfieldDescriptor:
350 Bitfield = o.Bitfield;
355 /// getStartLoc - Get the location of the first token of this operand.
356 SMLoc getStartLoc() const { return StartLoc; }
357 /// getEndLoc - Get the location of the last token of this operand.
358 SMLoc getEndLoc() const { return EndLoc; }
360 ARMCC::CondCodes getCondCode() const {
361 assert(Kind == CondCode && "Invalid access!");
365 unsigned getCoproc() const {
366 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
370 StringRef getToken() const {
371 assert(Kind == Token && "Invalid access!");
372 return StringRef(Tok.Data, Tok.Length);
375 unsigned getReg() const {
376 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
380 const SmallVectorImpl<unsigned> &getRegList() const {
381 assert((Kind == RegisterList || Kind == DPRRegisterList ||
382 Kind == SPRRegisterList) && "Invalid access!");
386 const MCExpr *getImm() const {
387 assert(Kind == Immediate && "Invalid access!");
391 ARM_MB::MemBOpt getMemBarrierOpt() const {
392 assert(Kind == MemBarrierOpt && "Invalid access!");
396 ARM_PROC::IFlags getProcIFlags() const {
397 assert(Kind == ProcIFlags && "Invalid access!");
401 unsigned getMSRMask() const {
402 assert(Kind == MSRMask && "Invalid access!");
406 bool isCoprocNum() const { return Kind == CoprocNum; }
407 bool isCoprocReg() const { return Kind == CoprocReg; }
408 bool isCondCode() const { return Kind == CondCode; }
409 bool isCCOut() const { return Kind == CCOut; }
410 bool isImm() const { return Kind == Immediate; }
411 bool isImm0_255() const {
412 if (Kind != Immediate)
414 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
415 if (!CE) return false;
416 int64_t Value = CE->getValue();
417 return Value >= 0 && Value < 256;
419 bool isImm0_7() const {
420 if (Kind != Immediate)
422 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
423 if (!CE) return false;
424 int64_t Value = CE->getValue();
425 return Value >= 0 && Value < 8;
427 bool isImm0_15() const {
428 if (Kind != Immediate)
430 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
431 if (!CE) return false;
432 int64_t Value = CE->getValue();
433 return Value >= 0 && Value < 16;
435 bool isImm0_31() const {
436 if (Kind != Immediate)
438 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
439 if (!CE) return false;
440 int64_t Value = CE->getValue();
441 return Value >= 0 && Value < 32;
443 bool isImm1_16() const {
444 if (Kind != Immediate)
446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
447 if (!CE) return false;
448 int64_t Value = CE->getValue();
449 return Value > 0 && Value < 17;
451 bool isImm1_32() const {
452 if (Kind != Immediate)
454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
455 if (!CE) return false;
456 int64_t Value = CE->getValue();
457 return Value > 0 && Value < 33;
459 bool isImm0_65535() const {
460 if (Kind != Immediate)
462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
463 if (!CE) return false;
464 int64_t Value = CE->getValue();
465 return Value >= 0 && Value < 65536;
467 bool isImm0_65535Expr() const {
468 if (Kind != Immediate)
470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
471 // If it's not a constant expression, it'll generate a fixup and be
473 if (!CE) return true;
474 int64_t Value = CE->getValue();
475 return Value >= 0 && Value < 65536;
477 bool isImm24bit() const {
478 if (Kind != Immediate)
480 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
481 if (!CE) return false;
482 int64_t Value = CE->getValue();
483 return Value >= 0 && Value <= 0xffffff;
485 bool isImmThumbSR() const {
486 if (Kind != Immediate)
488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
489 if (!CE) return false;
490 int64_t Value = CE->getValue();
491 return Value > 0 && Value < 33;
493 bool isPKHLSLImm() const {
494 if (Kind != Immediate)
496 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
497 if (!CE) return false;
498 int64_t Value = CE->getValue();
499 return Value >= 0 && Value < 32;
501 bool isPKHASRImm() const {
502 if (Kind != Immediate)
504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
505 if (!CE) return false;
506 int64_t Value = CE->getValue();
507 return Value > 0 && Value <= 32;
509 bool isARMSOImm() const {
510 if (Kind != Immediate)
512 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
513 if (!CE) return false;
514 int64_t Value = CE->getValue();
515 return ARM_AM::getSOImmVal(Value) != -1;
517 bool isT2SOImm() const {
518 if (Kind != Immediate)
520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
521 if (!CE) return false;
522 int64_t Value = CE->getValue();
523 return ARM_AM::getT2SOImmVal(Value) != -1;
525 bool isSetEndImm() const {
526 if (Kind != Immediate)
528 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
529 if (!CE) return false;
530 int64_t Value = CE->getValue();
531 return Value == 1 || Value == 0;
533 bool isReg() const { return Kind == Register; }
534 bool isRegList() const { return Kind == RegisterList; }
535 bool isDPRRegList() const { return Kind == DPRRegisterList; }
536 bool isSPRRegList() const { return Kind == SPRRegisterList; }
537 bool isToken() const { return Kind == Token; }
538 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
539 bool isMemory() const { return Kind == Memory; }
540 bool isShifterImm() const { return Kind == ShifterImmediate; }
541 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
542 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
543 bool isRotImm() const { return Kind == RotateImmediate; }
544 bool isBitfield() const { return Kind == BitfieldDescriptor; }
545 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
546 bool isPostIdxReg() const {
547 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
549 bool isMemNoOffset() const {
552 // No offset of any kind.
553 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
555 bool isAddrMode2() const {
558 // Check for register offset.
559 if (Mem.OffsetRegNum) return true;
560 // Immediate offset in range [-4095, 4095].
561 if (!Mem.OffsetImm) return true;
562 int64_t Val = Mem.OffsetImm->getValue();
563 return Val > -4096 && Val < 4096;
565 bool isAM2OffsetImm() const {
566 if (Kind != Immediate)
568 // Immediate offset in range [-4095, 4095].
569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570 if (!CE) return false;
571 int64_t Val = CE->getValue();
572 return Val > -4096 && Val < 4096;
574 bool isAddrMode3() const {
577 // No shifts are legal for AM3.
578 if (Mem.ShiftType != ARM_AM::no_shift) return false;
579 // Check for register offset.
580 if (Mem.OffsetRegNum) return true;
581 // Immediate offset in range [-255, 255].
582 if (!Mem.OffsetImm) return true;
583 int64_t Val = Mem.OffsetImm->getValue();
584 return Val > -256 && Val < 256;
586 bool isAM3Offset() const {
587 if (Kind != Immediate && Kind != PostIndexRegister)
589 if (Kind == PostIndexRegister)
590 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
591 // Immediate offset in range [-255, 255].
592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593 if (!CE) return false;
594 int64_t Val = CE->getValue();
595 // Special case, #-0 is INT32_MIN.
596 return (Val > -256 && Val < 256) || Val == INT32_MIN;
598 bool isAddrMode5() const {
601 // Check for register offset.
602 if (Mem.OffsetRegNum) return false;
603 // Immediate offset in range [-1020, 1020] and a multiple of 4.
604 if (!Mem.OffsetImm) return true;
605 int64_t Val = Mem.OffsetImm->getValue();
606 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0);
608 bool isMemRegOffset() const {
609 if (Kind != Memory || !Mem.OffsetRegNum)
613 bool isMemThumbRR() const {
614 // Thumb reg+reg addressing is simple. Just two registers, a base and
615 // an offset. No shifts, negations or any other complicating factors.
616 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
617 Mem.ShiftType != ARM_AM::no_shift)
621 bool isMemImm8Offset() const {
622 if (Kind != Memory || Mem.OffsetRegNum != 0)
624 // Immediate offset in range [-255, 255].
625 if (!Mem.OffsetImm) return true;
626 int64_t Val = Mem.OffsetImm->getValue();
627 return Val > -256 && Val < 256;
629 bool isMemImm12Offset() const {
630 // If we have an immediate that's not a constant, treat it as a label
631 // reference needing a fixup. If it is a constant, it's something else
633 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
636 if (Kind != Memory || Mem.OffsetRegNum != 0)
638 // Immediate offset in range [-4095, 4095].
639 if (!Mem.OffsetImm) return true;
640 int64_t Val = Mem.OffsetImm->getValue();
641 return Val > -4096 && Val < 4096;
643 bool isPostIdxImm8() const {
644 if (Kind != Immediate)
646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
647 if (!CE) return false;
648 int64_t Val = CE->getValue();
649 return Val > -256 && Val < 256;
652 bool isMSRMask() const { return Kind == MSRMask; }
653 bool isProcIFlags() const { return Kind == ProcIFlags; }
655 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
656 // Add as immediates when possible. Null MCExpr = 0.
658 Inst.addOperand(MCOperand::CreateImm(0));
659 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
660 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
662 Inst.addOperand(MCOperand::CreateExpr(Expr));
665 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
666 assert(N == 2 && "Invalid number of operands!");
667 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
668 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
669 Inst.addOperand(MCOperand::CreateReg(RegNum));
672 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
673 assert(N == 1 && "Invalid number of operands!");
674 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
677 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
678 assert(N == 1 && "Invalid number of operands!");
679 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
682 void addCCOutOperands(MCInst &Inst, unsigned N) const {
683 assert(N == 1 && "Invalid number of operands!");
684 Inst.addOperand(MCOperand::CreateReg(getReg()));
687 void addRegOperands(MCInst &Inst, unsigned N) const {
688 assert(N == 1 && "Invalid number of operands!");
689 Inst.addOperand(MCOperand::CreateReg(getReg()));
692 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
693 assert(N == 3 && "Invalid number of operands!");
694 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
695 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
696 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
697 Inst.addOperand(MCOperand::CreateImm(
698 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
701 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
702 assert(N == 2 && "Invalid number of operands!");
703 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
704 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
705 Inst.addOperand(MCOperand::CreateImm(
706 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
710 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
711 assert(N == 1 && "Invalid number of operands!");
712 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
716 void addRegListOperands(MCInst &Inst, unsigned N) const {
717 assert(N == 1 && "Invalid number of operands!");
718 const SmallVectorImpl<unsigned> &RegList = getRegList();
719 for (SmallVectorImpl<unsigned>::const_iterator
720 I = RegList.begin(), E = RegList.end(); I != E; ++I)
721 Inst.addOperand(MCOperand::CreateReg(*I));
724 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
725 addRegListOperands(Inst, N);
728 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
729 addRegListOperands(Inst, N);
732 void addRotImmOperands(MCInst &Inst, unsigned N) const {
733 assert(N == 1 && "Invalid number of operands!");
734 // Encoded as val>>3. The printer handles display as 8, 16, 24.
735 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
738 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
739 assert(N == 1 && "Invalid number of operands!");
740 // Munge the lsb/width into a bitfield mask.
741 unsigned lsb = Bitfield.LSB;
742 unsigned width = Bitfield.Width;
743 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
744 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
745 (32 - (lsb + width)));
746 Inst.addOperand(MCOperand::CreateImm(Mask));
749 void addImmOperands(MCInst &Inst, unsigned N) const {
750 assert(N == 1 && "Invalid number of operands!");
751 addExpr(Inst, getImm());
754 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
755 assert(N == 1 && "Invalid number of operands!");
756 addExpr(Inst, getImm());
759 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
760 assert(N == 1 && "Invalid number of operands!");
761 addExpr(Inst, getImm());
764 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
765 assert(N == 1 && "Invalid number of operands!");
766 addExpr(Inst, getImm());
769 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
770 assert(N == 1 && "Invalid number of operands!");
771 addExpr(Inst, getImm());
774 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
775 assert(N == 1 && "Invalid number of operands!");
776 // The constant encodes as the immediate-1, and we store in the instruction
777 // the bits as encoded, so subtract off one here.
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
782 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
783 assert(N == 1 && "Invalid number of operands!");
784 // The constant encodes as the immediate-1, and we store in the instruction
785 // the bits as encoded, so subtract off one here.
786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
787 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
790 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
791 assert(N == 1 && "Invalid number of operands!");
792 addExpr(Inst, getImm());
795 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
796 assert(N == 1 && "Invalid number of operands!");
797 addExpr(Inst, getImm());
800 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
801 assert(N == 1 && "Invalid number of operands!");
802 addExpr(Inst, getImm());
805 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
806 assert(N == 1 && "Invalid number of operands!");
807 // The constant encodes as the immediate, except for 32, which encodes as
809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810 unsigned Imm = CE->getValue();
811 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
814 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
815 assert(N == 1 && "Invalid number of operands!");
816 addExpr(Inst, getImm());
819 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
820 assert(N == 1 && "Invalid number of operands!");
821 // An ASR value of 32 encodes as 0, so that's how we want to add it to
822 // the instruction as well.
823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824 int Val = CE->getValue();
825 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
828 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
829 assert(N == 1 && "Invalid number of operands!");
830 addExpr(Inst, getImm());
833 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
834 assert(N == 1 && "Invalid number of operands!");
835 addExpr(Inst, getImm());
838 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
839 assert(N == 1 && "Invalid number of operands!");
840 addExpr(Inst, getImm());
843 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
844 assert(N == 1 && "Invalid number of operands!");
845 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
848 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
849 assert(N == 1 && "Invalid number of operands!");
850 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
853 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
854 assert(N == 3 && "Invalid number of operands!");
855 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
856 if (!Mem.OffsetRegNum) {
857 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
858 // Special case for #-0
859 if (Val == INT32_MIN) Val = 0;
860 if (Val < 0) Val = -Val;
861 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
863 // For register offset, we encode the shift type and negation flag
865 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
866 Mem.ShiftImm, Mem.ShiftType);
868 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
869 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
870 Inst.addOperand(MCOperand::CreateImm(Val));
873 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
874 assert(N == 2 && "Invalid number of operands!");
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 assert(CE && "non-constant AM2OffsetImm operand!");
877 int32_t Val = CE->getValue();
878 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
879 // Special case for #-0
880 if (Val == INT32_MIN) Val = 0;
881 if (Val < 0) Val = -Val;
882 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
883 Inst.addOperand(MCOperand::CreateReg(0));
884 Inst.addOperand(MCOperand::CreateImm(Val));
887 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
888 assert(N == 3 && "Invalid number of operands!");
889 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
890 if (!Mem.OffsetRegNum) {
891 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
892 // Special case for #-0
893 if (Val == INT32_MIN) Val = 0;
894 if (Val < 0) Val = -Val;
895 Val = ARM_AM::getAM3Opc(AddSub, Val);
897 // For register offset, we encode the shift type and negation flag
899 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
901 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
902 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
903 Inst.addOperand(MCOperand::CreateImm(Val));
906 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
907 assert(N == 2 && "Invalid number of operands!");
908 if (Kind == PostIndexRegister) {
910 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
911 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
912 Inst.addOperand(MCOperand::CreateImm(Val));
917 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
918 int32_t Val = CE->getValue();
919 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
920 // Special case for #-0
921 if (Val == INT32_MIN) Val = 0;
922 if (Val < 0) Val = -Val;
923 Val = ARM_AM::getAM3Opc(AddSub, Val);
924 Inst.addOperand(MCOperand::CreateReg(0));
925 Inst.addOperand(MCOperand::CreateImm(Val));
928 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
929 assert(N == 2 && "Invalid number of operands!");
930 // The lower two bits are always zero and as such are not encoded.
931 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
932 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
933 // Special case for #-0
934 if (Val == INT32_MIN) Val = 0;
935 if (Val < 0) Val = -Val;
936 Val = ARM_AM::getAM5Opc(AddSub, Val);
937 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
938 Inst.addOperand(MCOperand::CreateImm(Val));
941 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
942 assert(N == 2 && "Invalid number of operands!");
943 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
944 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
945 Inst.addOperand(MCOperand::CreateImm(Val));
948 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
949 assert(N == 2 && "Invalid number of operands!");
950 // If this is an immediate, it's a label reference.
951 if (Kind == Immediate) {
952 addExpr(Inst, getImm());
953 Inst.addOperand(MCOperand::CreateImm(0));
957 // Otherwise, it's a normal memory reg+offset.
958 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
959 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
960 Inst.addOperand(MCOperand::CreateImm(Val));
963 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
964 assert(N == 3 && "Invalid number of operands!");
965 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
966 Mem.ShiftImm, Mem.ShiftType);
967 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
968 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
969 Inst.addOperand(MCOperand::CreateImm(Val));
972 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
973 assert(N == 2 && "Invalid number of operands!");
974 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
975 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
978 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
979 assert(N == 1 && "Invalid number of operands!");
980 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
981 assert(CE && "non-constant post-idx-imm8 operand!");
982 int Imm = CE->getValue();
983 bool isAdd = Imm >= 0;
984 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
985 Inst.addOperand(MCOperand::CreateImm(Imm));
988 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
989 assert(N == 2 && "Invalid number of operands!");
990 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
991 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
994 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
995 assert(N == 2 && "Invalid number of operands!");
996 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
997 // The sign, shift type, and shift amount are encoded in a single operand
998 // using the AM2 encoding helpers.
999 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1000 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1001 PostIdxReg.ShiftTy);
1002 Inst.addOperand(MCOperand::CreateImm(Imm));
1005 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1006 assert(N == 1 && "Invalid number of operands!");
1007 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1010 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1011 assert(N == 1 && "Invalid number of operands!");
1012 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1015 virtual void print(raw_ostream &OS) const;
1017 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1018 ARMOperand *Op = new ARMOperand(CondCode);
1025 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1026 ARMOperand *Op = new ARMOperand(CoprocNum);
1027 Op->Cop.Val = CopVal;
1033 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1034 ARMOperand *Op = new ARMOperand(CoprocReg);
1035 Op->Cop.Val = CopVal;
1041 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1042 ARMOperand *Op = new ARMOperand(CCOut);
1043 Op->Reg.RegNum = RegNum;
1049 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1050 ARMOperand *Op = new ARMOperand(Token);
1051 Op->Tok.Data = Str.data();
1052 Op->Tok.Length = Str.size();
1058 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1059 ARMOperand *Op = new ARMOperand(Register);
1060 Op->Reg.RegNum = RegNum;
1066 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1071 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1072 Op->RegShiftedReg.ShiftTy = ShTy;
1073 Op->RegShiftedReg.SrcReg = SrcReg;
1074 Op->RegShiftedReg.ShiftReg = ShiftReg;
1075 Op->RegShiftedReg.ShiftImm = ShiftImm;
1081 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1085 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1086 Op->RegShiftedImm.ShiftTy = ShTy;
1087 Op->RegShiftedImm.SrcReg = SrcReg;
1088 Op->RegShiftedImm.ShiftImm = ShiftImm;
1094 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1096 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1097 Op->ShifterImm.isASR = isASR;
1098 Op->ShifterImm.Imm = Imm;
1104 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1105 ARMOperand *Op = new ARMOperand(RotateImmediate);
1106 Op->RotImm.Imm = Imm;
1112 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1114 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1115 Op->Bitfield.LSB = LSB;
1116 Op->Bitfield.Width = Width;
1123 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1124 SMLoc StartLoc, SMLoc EndLoc) {
1125 KindTy Kind = RegisterList;
1127 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1128 contains(Regs.front().first))
1129 Kind = DPRRegisterList;
1130 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1131 contains(Regs.front().first))
1132 Kind = SPRRegisterList;
1134 ARMOperand *Op = new ARMOperand(Kind);
1135 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1136 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1137 Op->Registers.push_back(I->first);
1138 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1139 Op->StartLoc = StartLoc;
1140 Op->EndLoc = EndLoc;
1144 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1145 ARMOperand *Op = new ARMOperand(Immediate);
1152 static ARMOperand *CreateMem(unsigned BaseRegNum,
1153 const MCConstantExpr *OffsetImm,
1154 unsigned OffsetRegNum,
1155 ARM_AM::ShiftOpc ShiftType,
1159 ARMOperand *Op = new ARMOperand(Memory);
1160 Op->Mem.BaseRegNum = BaseRegNum;
1161 Op->Mem.OffsetImm = OffsetImm;
1162 Op->Mem.OffsetRegNum = OffsetRegNum;
1163 Op->Mem.ShiftType = ShiftType;
1164 Op->Mem.ShiftImm = ShiftImm;
1165 Op->Mem.isNegative = isNegative;
1171 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1172 ARM_AM::ShiftOpc ShiftTy,
1175 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1176 Op->PostIdxReg.RegNum = RegNum;
1177 Op->PostIdxReg.isAdd = isAdd;
1178 Op->PostIdxReg.ShiftTy = ShiftTy;
1179 Op->PostIdxReg.ShiftImm = ShiftImm;
1185 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1186 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1187 Op->MBOpt.Val = Opt;
1193 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1194 ARMOperand *Op = new ARMOperand(ProcIFlags);
1195 Op->IFlags.Val = IFlags;
1201 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1202 ARMOperand *Op = new ARMOperand(MSRMask);
1203 Op->MMask.Val = MMask;
1210 } // end anonymous namespace.
1212 void ARMOperand::print(raw_ostream &OS) const {
1215 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1218 OS << "<ccout " << getReg() << ">";
1221 OS << "<coprocessor number: " << getCoproc() << ">";
1224 OS << "<coprocessor register: " << getCoproc() << ">";
1227 OS << "<mask: " << getMSRMask() << ">";
1230 getImm()->print(OS);
1233 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1237 << " base:" << Mem.BaseRegNum;
1240 case PostIndexRegister:
1241 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1242 << PostIdxReg.RegNum;
1243 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1244 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1245 << PostIdxReg.ShiftImm;
1249 OS << "<ARM_PROC::";
1250 unsigned IFlags = getProcIFlags();
1251 for (int i=2; i >= 0; --i)
1252 if (IFlags & (1 << i))
1253 OS << ARM_PROC::IFlagsToString(1 << i);
1258 OS << "<register " << getReg() << ">";
1260 case ShifterImmediate:
1261 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1262 << " #" << ShifterImm.Imm << ">";
1264 case ShiftedRegister:
1265 OS << "<so_reg_reg "
1266 << RegShiftedReg.SrcReg
1267 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1268 << ", " << RegShiftedReg.ShiftReg << ", "
1269 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1272 case ShiftedImmediate:
1273 OS << "<so_reg_imm "
1274 << RegShiftedImm.SrcReg
1275 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1276 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1279 case RotateImmediate:
1280 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1282 case BitfieldDescriptor:
1283 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1284 << ", width: " << Bitfield.Width << ">";
1287 case DPRRegisterList:
1288 case SPRRegisterList: {
1289 OS << "<register_list ";
1291 const SmallVectorImpl<unsigned> &RegList = getRegList();
1292 for (SmallVectorImpl<unsigned>::const_iterator
1293 I = RegList.begin(), E = RegList.end(); I != E; ) {
1295 if (++I < E) OS << ", ";
1302 OS << "'" << getToken() << "'";
1307 /// @name Auto-generated Match Functions
1310 static unsigned MatchRegisterName(StringRef Name);
1314 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1315 SMLoc &StartLoc, SMLoc &EndLoc) {
1316 RegNo = tryParseRegister();
1318 return (RegNo == (unsigned)-1);
1321 /// Try to parse a register name. The token must be an Identifier when called,
1322 /// and if it is a register name the token is eaten and the register number is
1323 /// returned. Otherwise return -1.
1325 int ARMAsmParser::tryParseRegister() {
1326 const AsmToken &Tok = Parser.getTok();
1327 if (Tok.isNot(AsmToken::Identifier)) return -1;
1329 // FIXME: Validate register for the current architecture; we have to do
1330 // validation later, so maybe there is no need for this here.
1331 std::string upperCase = Tok.getString().str();
1332 std::string lowerCase = LowercaseString(upperCase);
1333 unsigned RegNum = MatchRegisterName(lowerCase);
1335 RegNum = StringSwitch<unsigned>(lowerCase)
1336 .Case("r13", ARM::SP)
1337 .Case("r14", ARM::LR)
1338 .Case("r15", ARM::PC)
1339 .Case("ip", ARM::R12)
1342 if (!RegNum) return -1;
1344 Parser.Lex(); // Eat identifier token.
1348 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1349 // If a recoverable error occurs, return 1. If an irrecoverable error
1350 // occurs, return -1. An irrecoverable error is one where tokens have been
1351 // consumed in the process of trying to parse the shifter (i.e., when it is
1352 // indeed a shifter operand, but malformed).
1353 int ARMAsmParser::tryParseShiftRegister(
1354 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1355 SMLoc S = Parser.getTok().getLoc();
1356 const AsmToken &Tok = Parser.getTok();
1357 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1359 std::string upperCase = Tok.getString().str();
1360 std::string lowerCase = LowercaseString(upperCase);
1361 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1362 .Case("lsl", ARM_AM::lsl)
1363 .Case("lsr", ARM_AM::lsr)
1364 .Case("asr", ARM_AM::asr)
1365 .Case("ror", ARM_AM::ror)
1366 .Case("rrx", ARM_AM::rrx)
1367 .Default(ARM_AM::no_shift);
1369 if (ShiftTy == ARM_AM::no_shift)
1372 Parser.Lex(); // Eat the operator.
1374 // The source register for the shift has already been added to the
1375 // operand list, so we need to pop it off and combine it into the shifted
1376 // register operand instead.
1377 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1378 if (!PrevOp->isReg())
1379 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1380 int SrcReg = PrevOp->getReg();
1383 if (ShiftTy == ARM_AM::rrx) {
1384 // RRX Doesn't have an explicit shift amount. The encoder expects
1385 // the shift register to be the same as the source register. Seems odd,
1389 // Figure out if this is shifted by a constant or a register (for non-RRX).
1390 if (Parser.getTok().is(AsmToken::Hash)) {
1391 Parser.Lex(); // Eat hash.
1392 SMLoc ImmLoc = Parser.getTok().getLoc();
1393 const MCExpr *ShiftExpr = 0;
1394 if (getParser().ParseExpression(ShiftExpr)) {
1395 Error(ImmLoc, "invalid immediate shift value");
1398 // The expression must be evaluatable as an immediate.
1399 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1401 Error(ImmLoc, "invalid immediate shift value");
1404 // Range check the immediate.
1405 // lsl, ror: 0 <= imm <= 31
1406 // lsr, asr: 0 <= imm <= 32
1407 Imm = CE->getValue();
1409 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1410 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1411 Error(ImmLoc, "immediate shift value out of range");
1414 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1415 ShiftReg = tryParseRegister();
1416 SMLoc L = Parser.getTok().getLoc();
1417 if (ShiftReg == -1) {
1418 Error (L, "expected immediate or register in shift operand");
1422 Error (Parser.getTok().getLoc(),
1423 "expected immediate or register in shift operand");
1428 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1429 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1431 S, Parser.getTok().getLoc()));
1433 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1434 S, Parser.getTok().getLoc()));
1440 /// Try to parse a register name. The token must be an Identifier when called.
1441 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1442 /// if there is a "writeback". 'true' if it's not a register.
1444 /// TODO this is likely to change to allow different register types and or to
1445 /// parse for a specific register type.
1447 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1448 SMLoc S = Parser.getTok().getLoc();
1449 int RegNo = tryParseRegister();
1453 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1455 const AsmToken &ExclaimTok = Parser.getTok();
1456 if (ExclaimTok.is(AsmToken::Exclaim)) {
1457 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1458 ExclaimTok.getLoc()));
1459 Parser.Lex(); // Eat exclaim token
1465 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1466 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1468 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1469 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1471 switch (Name.size()) {
1474 if (Name[0] != CoprocOp)
1491 if (Name[0] != CoprocOp || Name[1] != '1')
1495 case '0': return 10;
1496 case '1': return 11;
1497 case '2': return 12;
1498 case '3': return 13;
1499 case '4': return 14;
1500 case '5': return 15;
1508 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1509 /// token must be an Identifier when called, and if it is a coprocessor
1510 /// number, the token is eaten and the operand is added to the operand list.
1511 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1512 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1513 SMLoc S = Parser.getTok().getLoc();
1514 const AsmToken &Tok = Parser.getTok();
1515 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1517 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1519 return MatchOperand_NoMatch;
1521 Parser.Lex(); // Eat identifier token.
1522 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1523 return MatchOperand_Success;
1526 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1527 /// token must be an Identifier when called, and if it is a coprocessor
1528 /// number, the token is eaten and the operand is added to the operand list.
1529 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1530 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1531 SMLoc S = Parser.getTok().getLoc();
1532 const AsmToken &Tok = Parser.getTok();
1533 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1535 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1537 return MatchOperand_NoMatch;
1539 Parser.Lex(); // Eat identifier token.
1540 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1541 return MatchOperand_Success;
1544 /// Parse a register list, return it if successful else return null. The first
1545 /// token must be a '{' when called.
1547 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1548 assert(Parser.getTok().is(AsmToken::LCurly) &&
1549 "Token is not a Left Curly Brace");
1550 SMLoc S = Parser.getTok().getLoc();
1552 // Read the rest of the registers in the list.
1553 unsigned PrevRegNum = 0;
1554 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1557 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1558 Parser.Lex(); // Eat non-identifier token.
1560 const AsmToken &RegTok = Parser.getTok();
1561 SMLoc RegLoc = RegTok.getLoc();
1562 if (RegTok.isNot(AsmToken::Identifier)) {
1563 Error(RegLoc, "register expected");
1567 int RegNum = tryParseRegister();
1569 Error(RegLoc, "register expected");
1574 int Reg = PrevRegNum;
1577 Registers.push_back(std::make_pair(Reg, RegLoc));
1578 } while (Reg != RegNum);
1580 Registers.push_back(std::make_pair(RegNum, RegLoc));
1583 PrevRegNum = RegNum;
1584 } while (Parser.getTok().is(AsmToken::Comma) ||
1585 Parser.getTok().is(AsmToken::Minus));
1587 // Process the right curly brace of the list.
1588 const AsmToken &RCurlyTok = Parser.getTok();
1589 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1590 Error(RCurlyTok.getLoc(), "'}' expected");
1594 SMLoc E = RCurlyTok.getLoc();
1595 Parser.Lex(); // Eat right curly brace token.
1597 // Verify the register list.
1598 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1599 RI = Registers.begin(), RE = Registers.end();
1601 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1602 bool EmittedWarning = false;
1604 DenseMap<unsigned, bool> RegMap;
1605 RegMap[HighRegNum] = true;
1607 for (++RI; RI != RE; ++RI) {
1608 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1609 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1612 Error(RegInfo.second, "register duplicated in register list");
1616 if (!EmittedWarning && Reg < HighRegNum)
1617 Warning(RegInfo.second,
1618 "register not in ascending order in register list");
1621 HighRegNum = std::max(Reg, HighRegNum);
1624 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1628 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1629 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1630 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1631 SMLoc S = Parser.getTok().getLoc();
1632 const AsmToken &Tok = Parser.getTok();
1633 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1634 StringRef OptStr = Tok.getString();
1636 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1637 .Case("sy", ARM_MB::SY)
1638 .Case("st", ARM_MB::ST)
1639 .Case("sh", ARM_MB::ISH)
1640 .Case("ish", ARM_MB::ISH)
1641 .Case("shst", ARM_MB::ISHST)
1642 .Case("ishst", ARM_MB::ISHST)
1643 .Case("nsh", ARM_MB::NSH)
1644 .Case("un", ARM_MB::NSH)
1645 .Case("nshst", ARM_MB::NSHST)
1646 .Case("unst", ARM_MB::NSHST)
1647 .Case("osh", ARM_MB::OSH)
1648 .Case("oshst", ARM_MB::OSHST)
1652 return MatchOperand_NoMatch;
1654 Parser.Lex(); // Eat identifier token.
1655 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1656 return MatchOperand_Success;
1659 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1660 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1661 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1662 SMLoc S = Parser.getTok().getLoc();
1663 const AsmToken &Tok = Parser.getTok();
1664 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1665 StringRef IFlagsStr = Tok.getString();
1667 unsigned IFlags = 0;
1668 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1669 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1670 .Case("a", ARM_PROC::A)
1671 .Case("i", ARM_PROC::I)
1672 .Case("f", ARM_PROC::F)
1675 // If some specific iflag is already set, it means that some letter is
1676 // present more than once, this is not acceptable.
1677 if (Flag == ~0U || (IFlags & Flag))
1678 return MatchOperand_NoMatch;
1683 Parser.Lex(); // Eat identifier token.
1684 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1685 return MatchOperand_Success;
1688 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1689 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1690 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1691 SMLoc S = Parser.getTok().getLoc();
1692 const AsmToken &Tok = Parser.getTok();
1693 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1694 StringRef Mask = Tok.getString();
1696 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1697 size_t Start = 0, Next = Mask.find('_');
1698 StringRef Flags = "";
1699 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1700 if (Next != StringRef::npos)
1701 Flags = Mask.slice(Next+1, Mask.size());
1703 // FlagsVal contains the complete mask:
1705 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1706 unsigned FlagsVal = 0;
1708 if (SpecReg == "apsr") {
1709 FlagsVal = StringSwitch<unsigned>(Flags)
1710 .Case("nzcvq", 0x8) // same as CPSR_f
1711 .Case("g", 0x4) // same as CPSR_s
1712 .Case("nzcvqg", 0xc) // same as CPSR_fs
1715 if (FlagsVal == ~0U) {
1717 return MatchOperand_NoMatch;
1719 FlagsVal = 0; // No flag
1721 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1722 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1724 for (int i = 0, e = Flags.size(); i != e; ++i) {
1725 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1732 // If some specific flag is already set, it means that some letter is
1733 // present more than once, this is not acceptable.
1734 if (FlagsVal == ~0U || (FlagsVal & Flag))
1735 return MatchOperand_NoMatch;
1738 } else // No match for special register.
1739 return MatchOperand_NoMatch;
1741 // Special register without flags are equivalent to "fc" flags.
1745 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1746 if (SpecReg == "spsr")
1749 Parser.Lex(); // Eat identifier token.
1750 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1751 return MatchOperand_Success;
1754 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1755 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1756 int Low, int High) {
1757 const AsmToken &Tok = Parser.getTok();
1758 if (Tok.isNot(AsmToken::Identifier)) {
1759 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1760 return MatchOperand_ParseFail;
1762 StringRef ShiftName = Tok.getString();
1763 std::string LowerOp = LowercaseString(Op);
1764 std::string UpperOp = UppercaseString(Op);
1765 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1766 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1767 return MatchOperand_ParseFail;
1769 Parser.Lex(); // Eat shift type token.
1771 // There must be a '#' and a shift amount.
1772 if (Parser.getTok().isNot(AsmToken::Hash)) {
1773 Error(Parser.getTok().getLoc(), "'#' expected");
1774 return MatchOperand_ParseFail;
1776 Parser.Lex(); // Eat hash token.
1778 const MCExpr *ShiftAmount;
1779 SMLoc Loc = Parser.getTok().getLoc();
1780 if (getParser().ParseExpression(ShiftAmount)) {
1781 Error(Loc, "illegal expression");
1782 return MatchOperand_ParseFail;
1784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1786 Error(Loc, "constant expression expected");
1787 return MatchOperand_ParseFail;
1789 int Val = CE->getValue();
1790 if (Val < Low || Val > High) {
1791 Error(Loc, "immediate value out of range");
1792 return MatchOperand_ParseFail;
1795 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1797 return MatchOperand_Success;
1800 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1801 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1802 const AsmToken &Tok = Parser.getTok();
1803 SMLoc S = Tok.getLoc();
1804 if (Tok.isNot(AsmToken::Identifier)) {
1805 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1806 return MatchOperand_ParseFail;
1808 int Val = StringSwitch<int>(Tok.getString())
1812 Parser.Lex(); // Eat the token.
1815 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1816 return MatchOperand_ParseFail;
1818 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1820 S, Parser.getTok().getLoc()));
1821 return MatchOperand_Success;
1824 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1825 /// instructions. Legal values are:
1826 /// lsl #n 'n' in [0,31]
1827 /// asr #n 'n' in [1,32]
1828 /// n == 32 encoded as n == 0.
1829 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1830 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1831 const AsmToken &Tok = Parser.getTok();
1832 SMLoc S = Tok.getLoc();
1833 if (Tok.isNot(AsmToken::Identifier)) {
1834 Error(S, "shift operator 'asr' or 'lsl' expected");
1835 return MatchOperand_ParseFail;
1837 StringRef ShiftName = Tok.getString();
1839 if (ShiftName == "lsl" || ShiftName == "LSL")
1841 else if (ShiftName == "asr" || ShiftName == "ASR")
1844 Error(S, "shift operator 'asr' or 'lsl' expected");
1845 return MatchOperand_ParseFail;
1847 Parser.Lex(); // Eat the operator.
1849 // A '#' and a shift amount.
1850 if (Parser.getTok().isNot(AsmToken::Hash)) {
1851 Error(Parser.getTok().getLoc(), "'#' expected");
1852 return MatchOperand_ParseFail;
1854 Parser.Lex(); // Eat hash token.
1856 const MCExpr *ShiftAmount;
1857 SMLoc E = Parser.getTok().getLoc();
1858 if (getParser().ParseExpression(ShiftAmount)) {
1859 Error(E, "malformed shift expression");
1860 return MatchOperand_ParseFail;
1862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1864 Error(E, "shift amount must be an immediate");
1865 return MatchOperand_ParseFail;
1868 int64_t Val = CE->getValue();
1870 // Shift amount must be in [1,32]
1871 if (Val < 1 || Val > 32) {
1872 Error(E, "'asr' shift amount must be in range [1,32]");
1873 return MatchOperand_ParseFail;
1875 // asr #32 encoded as asr #0.
1876 if (Val == 32) Val = 0;
1878 // Shift amount must be in [1,32]
1879 if (Val < 0 || Val > 31) {
1880 Error(E, "'lsr' shift amount must be in range [0,31]");
1881 return MatchOperand_ParseFail;
1885 E = Parser.getTok().getLoc();
1886 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1888 return MatchOperand_Success;
1891 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1892 /// of instructions. Legal values are:
1893 /// ror #n 'n' in {0, 8, 16, 24}
1894 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1895 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1896 const AsmToken &Tok = Parser.getTok();
1897 SMLoc S = Tok.getLoc();
1898 if (Tok.isNot(AsmToken::Identifier)) {
1899 Error(S, "rotate operator 'ror' expected");
1900 return MatchOperand_ParseFail;
1902 StringRef ShiftName = Tok.getString();
1903 if (ShiftName != "ror" && ShiftName != "ROR") {
1904 Error(S, "rotate operator 'ror' expected");
1905 return MatchOperand_ParseFail;
1907 Parser.Lex(); // Eat the operator.
1909 // A '#' and a rotate amount.
1910 if (Parser.getTok().isNot(AsmToken::Hash)) {
1911 Error(Parser.getTok().getLoc(), "'#' expected");
1912 return MatchOperand_ParseFail;
1914 Parser.Lex(); // Eat hash token.
1916 const MCExpr *ShiftAmount;
1917 SMLoc E = Parser.getTok().getLoc();
1918 if (getParser().ParseExpression(ShiftAmount)) {
1919 Error(E, "malformed rotate expression");
1920 return MatchOperand_ParseFail;
1922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1924 Error(E, "rotate amount must be an immediate");
1925 return MatchOperand_ParseFail;
1928 int64_t Val = CE->getValue();
1929 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1930 // normally, zero is represented in asm by omitting the rotate operand
1932 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1933 Error(E, "'ror' rotate amount must be 8, 16, or 24");
1934 return MatchOperand_ParseFail;
1937 E = Parser.getTok().getLoc();
1938 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1940 return MatchOperand_Success;
1943 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1944 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1945 SMLoc S = Parser.getTok().getLoc();
1946 // The bitfield descriptor is really two operands, the LSB and the width.
1947 if (Parser.getTok().isNot(AsmToken::Hash)) {
1948 Error(Parser.getTok().getLoc(), "'#' expected");
1949 return MatchOperand_ParseFail;
1951 Parser.Lex(); // Eat hash token.
1953 const MCExpr *LSBExpr;
1954 SMLoc E = Parser.getTok().getLoc();
1955 if (getParser().ParseExpression(LSBExpr)) {
1956 Error(E, "malformed immediate expression");
1957 return MatchOperand_ParseFail;
1959 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1961 Error(E, "'lsb' operand must be an immediate");
1962 return MatchOperand_ParseFail;
1965 int64_t LSB = CE->getValue();
1966 // The LSB must be in the range [0,31]
1967 if (LSB < 0 || LSB > 31) {
1968 Error(E, "'lsb' operand must be in the range [0,31]");
1969 return MatchOperand_ParseFail;
1971 E = Parser.getTok().getLoc();
1973 // Expect another immediate operand.
1974 if (Parser.getTok().isNot(AsmToken::Comma)) {
1975 Error(Parser.getTok().getLoc(), "too few operands");
1976 return MatchOperand_ParseFail;
1978 Parser.Lex(); // Eat hash token.
1979 if (Parser.getTok().isNot(AsmToken::Hash)) {
1980 Error(Parser.getTok().getLoc(), "'#' expected");
1981 return MatchOperand_ParseFail;
1983 Parser.Lex(); // Eat hash token.
1985 const MCExpr *WidthExpr;
1986 if (getParser().ParseExpression(WidthExpr)) {
1987 Error(E, "malformed immediate expression");
1988 return MatchOperand_ParseFail;
1990 CE = dyn_cast<MCConstantExpr>(WidthExpr);
1992 Error(E, "'width' operand must be an immediate");
1993 return MatchOperand_ParseFail;
1996 int64_t Width = CE->getValue();
1997 // The LSB must be in the range [1,32-lsb]
1998 if (Width < 1 || Width > 32 - LSB) {
1999 Error(E, "'width' operand must be in the range [1,32-lsb]");
2000 return MatchOperand_ParseFail;
2002 E = Parser.getTok().getLoc();
2004 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2006 return MatchOperand_Success;
2009 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2010 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2011 // Check for a post-index addressing register operand. Specifically:
2012 // postidx_reg := '+' register {, shift}
2013 // | '-' register {, shift}
2014 // | register {, shift}
2016 // This method must return MatchOperand_NoMatch without consuming any tokens
2017 // in the case where there is no match, as other alternatives take other
2019 AsmToken Tok = Parser.getTok();
2020 SMLoc S = Tok.getLoc();
2021 bool haveEaten = false;
2024 if (Tok.is(AsmToken::Plus)) {
2025 Parser.Lex(); // Eat the '+' token.
2027 } else if (Tok.is(AsmToken::Minus)) {
2028 Parser.Lex(); // Eat the '-' token.
2032 if (Parser.getTok().is(AsmToken::Identifier))
2033 Reg = tryParseRegister();
2036 return MatchOperand_NoMatch;
2037 Error(Parser.getTok().getLoc(), "register expected");
2038 return MatchOperand_ParseFail;
2040 SMLoc E = Parser.getTok().getLoc();
2042 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2043 unsigned ShiftImm = 0;
2044 if (Parser.getTok().is(AsmToken::Comma)) {
2045 Parser.Lex(); // Eat the ','.
2046 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2047 return MatchOperand_ParseFail;
2050 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2053 return MatchOperand_Success;
2056 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2057 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2058 // Check for a post-index addressing register operand. Specifically:
2059 // am3offset := '+' register
2066 // This method must return MatchOperand_NoMatch without consuming any tokens
2067 // in the case where there is no match, as other alternatives take other
2069 AsmToken Tok = Parser.getTok();
2070 SMLoc S = Tok.getLoc();
2072 // Do immediates first, as we always parse those if we have a '#'.
2073 if (Parser.getTok().is(AsmToken::Hash)) {
2074 Parser.Lex(); // Eat the '#'.
2075 // Explicitly look for a '-', as we need to encode negative zero
2077 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2078 const MCExpr *Offset;
2079 if (getParser().ParseExpression(Offset))
2080 return MatchOperand_ParseFail;
2081 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2083 Error(S, "constant expression expected");
2084 return MatchOperand_ParseFail;
2086 SMLoc E = Tok.getLoc();
2087 // Negative zero is encoded as the flag value INT32_MIN.
2088 int32_t Val = CE->getValue();
2089 if (isNegative && Val == 0)
2093 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2095 return MatchOperand_Success;
2099 bool haveEaten = false;
2102 if (Tok.is(AsmToken::Plus)) {
2103 Parser.Lex(); // Eat the '+' token.
2105 } else if (Tok.is(AsmToken::Minus)) {
2106 Parser.Lex(); // Eat the '-' token.
2110 if (Parser.getTok().is(AsmToken::Identifier))
2111 Reg = tryParseRegister();
2114 return MatchOperand_NoMatch;
2115 Error(Parser.getTok().getLoc(), "register expected");
2116 return MatchOperand_ParseFail;
2118 SMLoc E = Parser.getTok().getLoc();
2120 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2123 return MatchOperand_Success;
2126 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2127 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2128 /// when they refer multiple MIOperands inside a single one.
2130 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2131 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2132 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2134 // Create a writeback register dummy placeholder.
2135 Inst.addOperand(MCOperand::CreateImm(0));
2137 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2138 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2142 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2143 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2144 /// when they refer multiple MIOperands inside a single one.
2146 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2147 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2148 // Create a writeback register dummy placeholder.
2149 Inst.addOperand(MCOperand::CreateImm(0));
2150 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2151 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2152 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2156 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2157 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2158 /// when they refer multiple MIOperands inside a single one.
2160 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2161 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2162 // Create a writeback register dummy placeholder.
2163 Inst.addOperand(MCOperand::CreateImm(0));
2164 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2165 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2166 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2170 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2171 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2172 /// when they refer multiple MIOperands inside a single one.
2174 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2175 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2176 // Create a writeback register dummy placeholder.
2177 Inst.addOperand(MCOperand::CreateImm(0));
2178 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2179 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2180 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2184 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2185 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2186 /// when they refer multiple MIOperands inside a single one.
2188 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2189 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2191 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2192 // Create a writeback register dummy placeholder.
2193 Inst.addOperand(MCOperand::CreateImm(0));
2195 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2197 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2199 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2203 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2204 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2205 /// when they refer multiple MIOperands inside a single one.
2207 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2208 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2210 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2211 // Create a writeback register dummy placeholder.
2212 Inst.addOperand(MCOperand::CreateImm(0));
2214 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2216 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2218 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2222 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2223 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2224 /// when they refer multiple MIOperands inside a single one.
2226 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2227 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2228 // Create a writeback register dummy placeholder.
2229 Inst.addOperand(MCOperand::CreateImm(0));
2231 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2233 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2235 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2237 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2241 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2242 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2243 /// when they refer multiple MIOperands inside a single one.
2245 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2246 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2247 // Create a writeback register dummy placeholder.
2248 Inst.addOperand(MCOperand::CreateImm(0));
2250 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2252 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2254 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2256 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2260 /// cvtLdrdPre - Convert parsed operands to MCInst.
2261 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2262 /// when they refer multiple MIOperands inside a single one.
2264 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2265 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2267 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2268 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2269 // Create a writeback register dummy placeholder.
2270 Inst.addOperand(MCOperand::CreateImm(0));
2272 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2274 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2278 /// cvtStrdPre - Convert parsed operands to MCInst.
2279 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2280 /// when they refer multiple MIOperands inside a single one.
2282 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2283 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2284 // Create a writeback register dummy placeholder.
2285 Inst.addOperand(MCOperand::CreateImm(0));
2287 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2288 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2290 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2292 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2296 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2297 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2298 /// when they refer multiple MIOperands inside a single one.
2300 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2301 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2302 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2303 // Create a writeback register dummy placeholder.
2304 Inst.addOperand(MCOperand::CreateImm(0));
2305 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2306 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2311 /// Parse an ARM memory expression, return false if successful else return true
2312 /// or an error. The first token must be a '[' when called.
2314 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2316 assert(Parser.getTok().is(AsmToken::LBrac) &&
2317 "Token is not a Left Bracket");
2318 S = Parser.getTok().getLoc();
2319 Parser.Lex(); // Eat left bracket token.
2321 const AsmToken &BaseRegTok = Parser.getTok();
2322 int BaseRegNum = tryParseRegister();
2323 if (BaseRegNum == -1)
2324 return Error(BaseRegTok.getLoc(), "register expected");
2326 // The next token must either be a comma or a closing bracket.
2327 const AsmToken &Tok = Parser.getTok();
2328 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2329 return Error(Tok.getLoc(), "malformed memory operand");
2331 if (Tok.is(AsmToken::RBrac)) {
2333 Parser.Lex(); // Eat right bracket token.
2335 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2341 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2342 Parser.Lex(); // Eat the comma.
2344 // If we have a '#' it's an immediate offset, else assume it's a register
2346 if (Parser.getTok().is(AsmToken::Hash)) {
2347 Parser.Lex(); // Eat the '#'.
2348 E = Parser.getTok().getLoc();
2350 // FIXME: Special case #-0 so we can correctly set the U bit.
2352 const MCExpr *Offset;
2353 if (getParser().ParseExpression(Offset))
2356 // The expression has to be a constant. Memory references with relocations
2357 // don't come through here, as they use the <label> forms of the relevant
2359 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2361 return Error (E, "constant expression expected");
2363 // Now we should have the closing ']'
2364 E = Parser.getTok().getLoc();
2365 if (Parser.getTok().isNot(AsmToken::RBrac))
2366 return Error(E, "']' expected");
2367 Parser.Lex(); // Eat right bracket token.
2369 // Don't worry about range checking the value here. That's handled by
2370 // the is*() predicates.
2371 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2372 ARM_AM::no_shift, 0, false, S,E));
2374 // If there's a pre-indexing writeback marker, '!', just add it as a token
2376 if (Parser.getTok().is(AsmToken::Exclaim)) {
2377 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2378 Parser.Lex(); // Eat the '!'.
2384 // The register offset is optionally preceded by a '+' or '-'
2385 bool isNegative = false;
2386 if (Parser.getTok().is(AsmToken::Minus)) {
2388 Parser.Lex(); // Eat the '-'.
2389 } else if (Parser.getTok().is(AsmToken::Plus)) {
2391 Parser.Lex(); // Eat the '+'.
2394 E = Parser.getTok().getLoc();
2395 int OffsetRegNum = tryParseRegister();
2396 if (OffsetRegNum == -1)
2397 return Error(E, "register expected");
2399 // If there's a shift operator, handle it.
2400 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2401 unsigned ShiftImm = 0;
2402 if (Parser.getTok().is(AsmToken::Comma)) {
2403 Parser.Lex(); // Eat the ','.
2404 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2408 // Now we should have the closing ']'
2409 E = Parser.getTok().getLoc();
2410 if (Parser.getTok().isNot(AsmToken::RBrac))
2411 return Error(E, "']' expected");
2412 Parser.Lex(); // Eat right bracket token.
2414 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2415 ShiftType, ShiftImm, isNegative,
2418 // If there's a pre-indexing writeback marker, '!', just add it as a token
2420 if (Parser.getTok().is(AsmToken::Exclaim)) {
2421 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2422 Parser.Lex(); // Eat the '!'.
2428 /// parseMemRegOffsetShift - one of these two:
2429 /// ( lsl | lsr | asr | ror ) , # shift_amount
2431 /// return true if it parses a shift otherwise it returns false.
2432 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2434 SMLoc Loc = Parser.getTok().getLoc();
2435 const AsmToken &Tok = Parser.getTok();
2436 if (Tok.isNot(AsmToken::Identifier))
2438 StringRef ShiftName = Tok.getString();
2439 if (ShiftName == "lsl" || ShiftName == "LSL")
2441 else if (ShiftName == "lsr" || ShiftName == "LSR")
2443 else if (ShiftName == "asr" || ShiftName == "ASR")
2445 else if (ShiftName == "ror" || ShiftName == "ROR")
2447 else if (ShiftName == "rrx" || ShiftName == "RRX")
2450 return Error(Loc, "illegal shift operator");
2451 Parser.Lex(); // Eat shift type token.
2453 // rrx stands alone.
2455 if (St != ARM_AM::rrx) {
2456 Loc = Parser.getTok().getLoc();
2457 // A '#' and a shift amount.
2458 const AsmToken &HashTok = Parser.getTok();
2459 if (HashTok.isNot(AsmToken::Hash))
2460 return Error(HashTok.getLoc(), "'#' expected");
2461 Parser.Lex(); // Eat hash token.
2464 if (getParser().ParseExpression(Expr))
2466 // Range check the immediate.
2467 // lsl, ror: 0 <= imm <= 31
2468 // lsr, asr: 0 <= imm <= 32
2469 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2471 return Error(Loc, "shift amount must be an immediate");
2472 int64_t Imm = CE->getValue();
2474 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2475 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2476 return Error(Loc, "immediate shift value out of range");
2483 /// Parse a arm instruction operand. For now this parses the operand regardless
2484 /// of the mnemonic.
2485 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2486 StringRef Mnemonic) {
2489 // Check if the current operand has a custom associated parser, if so, try to
2490 // custom parse the operand, or fallback to the general approach.
2491 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2492 if (ResTy == MatchOperand_Success)
2494 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2495 // there was a match, but an error occurred, in which case, just return that
2496 // the operand parsing failed.
2497 if (ResTy == MatchOperand_ParseFail)
2500 switch (getLexer().getKind()) {
2502 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2504 case AsmToken::Identifier: {
2505 if (!tryParseRegisterWithWriteBack(Operands))
2507 int Res = tryParseShiftRegister(Operands);
2508 if (Res == 0) // success
2510 else if (Res == -1) // irrecoverable error
2513 // Fall though for the Identifier case that is not a register or a
2516 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2517 case AsmToken::Dot: { // . as a branch target
2518 // This was not a register so parse other operands that start with an
2519 // identifier (like labels) as expressions and create them as immediates.
2520 const MCExpr *IdVal;
2521 S = Parser.getTok().getLoc();
2522 if (getParser().ParseExpression(IdVal))
2524 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2525 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2528 case AsmToken::LBrac:
2529 return parseMemory(Operands);
2530 case AsmToken::LCurly:
2531 return parseRegisterList(Operands);
2532 case AsmToken::Hash:
2533 // #42 -> immediate.
2534 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2535 S = Parser.getTok().getLoc();
2537 const MCExpr *ImmVal;
2538 if (getParser().ParseExpression(ImmVal))
2540 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2541 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2543 case AsmToken::Colon: {
2544 // ":lower16:" and ":upper16:" expression prefixes
2545 // FIXME: Check it's an expression prefix,
2546 // e.g. (FOO - :lower16:BAR) isn't legal.
2547 ARMMCExpr::VariantKind RefKind;
2548 if (parsePrefix(RefKind))
2551 const MCExpr *SubExprVal;
2552 if (getParser().ParseExpression(SubExprVal))
2555 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2557 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2558 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2564 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2565 // :lower16: and :upper16:.
2566 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2567 RefKind = ARMMCExpr::VK_ARM_None;
2569 // :lower16: and :upper16: modifiers
2570 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2571 Parser.Lex(); // Eat ':'
2573 if (getLexer().isNot(AsmToken::Identifier)) {
2574 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2578 StringRef IDVal = Parser.getTok().getIdentifier();
2579 if (IDVal == "lower16") {
2580 RefKind = ARMMCExpr::VK_ARM_LO16;
2581 } else if (IDVal == "upper16") {
2582 RefKind = ARMMCExpr::VK_ARM_HI16;
2584 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2589 if (getLexer().isNot(AsmToken::Colon)) {
2590 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2593 Parser.Lex(); // Eat the last ':'
2598 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2599 MCSymbolRefExpr::VariantKind Variant) {
2600 // Recurse over the given expression, rebuilding it to apply the given variant
2601 // to the leftmost symbol.
2602 if (Variant == MCSymbolRefExpr::VK_None)
2605 switch (E->getKind()) {
2606 case MCExpr::Target:
2607 llvm_unreachable("Can't handle target expr yet");
2608 case MCExpr::Constant:
2609 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2611 case MCExpr::SymbolRef: {
2612 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2614 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2617 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2621 llvm_unreachable("Can't handle unary expressions yet");
2623 case MCExpr::Binary: {
2624 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2625 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2626 const MCExpr *RHS = BE->getRHS();
2630 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2634 assert(0 && "Invalid expression kind!");
2638 /// \brief Given a mnemonic, split out possible predication code and carry
2639 /// setting letters to form a canonical mnemonic and flags.
2641 // FIXME: Would be nice to autogen this.
2642 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2643 unsigned &PredicationCode,
2645 unsigned &ProcessorIMod) {
2646 PredicationCode = ARMCC::AL;
2647 CarrySetting = false;
2650 // Ignore some mnemonics we know aren't predicated forms.
2652 // FIXME: Would be nice to autogen this.
2653 if ((Mnemonic == "movs" && isThumb()) ||
2654 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2655 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2656 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2657 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2658 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2659 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2660 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2663 // First, split out any predication code. Ignore mnemonics we know aren't
2664 // predicated but do have a carry-set and so weren't caught above.
2665 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2666 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2667 Mnemonic != "umlals" && Mnemonic != "umulls") {
2668 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2669 .Case("eq", ARMCC::EQ)
2670 .Case("ne", ARMCC::NE)
2671 .Case("hs", ARMCC::HS)
2672 .Case("cs", ARMCC::HS)
2673 .Case("lo", ARMCC::LO)
2674 .Case("cc", ARMCC::LO)
2675 .Case("mi", ARMCC::MI)
2676 .Case("pl", ARMCC::PL)
2677 .Case("vs", ARMCC::VS)
2678 .Case("vc", ARMCC::VC)
2679 .Case("hi", ARMCC::HI)
2680 .Case("ls", ARMCC::LS)
2681 .Case("ge", ARMCC::GE)
2682 .Case("lt", ARMCC::LT)
2683 .Case("gt", ARMCC::GT)
2684 .Case("le", ARMCC::LE)
2685 .Case("al", ARMCC::AL)
2688 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2689 PredicationCode = CC;
2693 // Next, determine if we have a carry setting bit. We explicitly ignore all
2694 // the instructions we know end in 's'.
2695 if (Mnemonic.endswith("s") &&
2696 !(Mnemonic == "cps" || Mnemonic == "mls" ||
2697 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2698 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2699 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2700 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
2701 (Mnemonic == "movs" && isThumb()))) {
2702 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2703 CarrySetting = true;
2706 // The "cps" instruction can have a interrupt mode operand which is glued into
2707 // the mnemonic. Check if this is the case, split it and parse the imod op
2708 if (Mnemonic.startswith("cps")) {
2709 // Split out any imod code.
2711 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2712 .Case("ie", ARM_PROC::IE)
2713 .Case("id", ARM_PROC::ID)
2716 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2717 ProcessorIMod = IMod;
2724 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2725 /// inclusion of carry set or predication code operands.
2727 // FIXME: It would be nice to autogen this.
2729 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2730 bool &CanAcceptPredicationCode) {
2731 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2732 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2733 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2734 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2735 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2736 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2737 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2738 Mnemonic == "eor" || Mnemonic == "smlal" ||
2739 // FIXME: We need a better way. This really confused Thumb2
2740 // parsing for 'mov'.
2741 (Mnemonic == "mov" && !isThumbOne())) {
2742 CanAcceptCarrySet = true;
2744 CanAcceptCarrySet = false;
2747 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2748 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2749 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2750 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2751 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2752 Mnemonic == "setend" ||
2753 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) ||
2754 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs"))
2756 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2757 CanAcceptPredicationCode = false;
2759 CanAcceptPredicationCode = true;
2763 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2764 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2765 CanAcceptPredicationCode = false;
2768 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
2769 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2771 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2772 // another does not. Specifically, the MOVW instruction does not. So we
2773 // special case it here and remove the defaulted (non-setting) cc_out
2774 // operand if that's the instruction we're trying to match.
2776 // We do this as post-processing of the explicit operands rather than just
2777 // conditionally adding the cc_out in the first place because we need
2778 // to check the type of the parsed immediate operand.
2779 if (Mnemonic == "mov" && Operands.size() > 4 &&
2780 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2781 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2782 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2785 // Register-register 'add' for thumb does not have a cc_out operand
2786 // when there are only two register operands.
2787 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
2788 static_cast<ARMOperand*>(Operands[3])->isReg() &&
2789 static_cast<ARMOperand*>(Operands[4])->isReg() &&
2790 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
2796 /// Parse an arm instruction mnemonic followed by its operands.
2797 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2798 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2799 // Create the leading tokens for the mnemonic, split by '.' characters.
2800 size_t Start = 0, Next = Name.find('.');
2801 StringRef Mnemonic = Name.slice(Start, Next);
2803 // Split out the predication code and carry setting flag from the mnemonic.
2804 unsigned PredicationCode;
2805 unsigned ProcessorIMod;
2807 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2810 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2812 // FIXME: This is all a pretty gross hack. We should automatically handle
2813 // optional operands like this via tblgen.
2815 // Next, add the CCOut and ConditionCode operands, if needed.
2817 // For mnemonics which can ever incorporate a carry setting bit or predication
2818 // code, our matching model involves us always generating CCOut and
2819 // ConditionCode operands to match the mnemonic "as written" and then we let
2820 // the matcher deal with finding the right instruction or generating an
2821 // appropriate error.
2822 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2823 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2825 // If we had a carry-set on an instruction that can't do that, issue an
2827 if (!CanAcceptCarrySet && CarrySetting) {
2828 Parser.EatToEndOfStatement();
2829 return Error(NameLoc, "instruction '" + Mnemonic +
2830 "' can not set flags, but 's' suffix specified");
2832 // If we had a predication code on an instruction that can't do that, issue an
2834 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2835 Parser.EatToEndOfStatement();
2836 return Error(NameLoc, "instruction '" + Mnemonic +
2837 "' is not predicable, but condition code specified");
2840 // Add the carry setting operand, if necessary.
2842 // FIXME: It would be awesome if we could somehow invent a location such that
2843 // match errors on this operand would print a nice diagnostic about how the
2844 // 's' character in the mnemonic resulted in a CCOut operand.
2845 if (CanAcceptCarrySet)
2846 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2849 // Add the predication code operand, if necessary.
2850 if (CanAcceptPredicationCode) {
2851 Operands.push_back(ARMOperand::CreateCondCode(
2852 ARMCC::CondCodes(PredicationCode), NameLoc));
2855 // Add the processor imod operand, if necessary.
2856 if (ProcessorIMod) {
2857 Operands.push_back(ARMOperand::CreateImm(
2858 MCConstantExpr::Create(ProcessorIMod, getContext()),
2861 // This mnemonic can't ever accept a imod, but the user wrote
2862 // one (or misspelled another mnemonic).
2864 // FIXME: Issue a nice error.
2867 // Add the remaining tokens in the mnemonic.
2868 while (Next != StringRef::npos) {
2870 Next = Name.find('.', Start + 1);
2871 StringRef ExtraToken = Name.slice(Start, Next);
2873 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2876 // Read the remaining operands.
2877 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2878 // Read the first operand.
2879 if (parseOperand(Operands, Mnemonic)) {
2880 Parser.EatToEndOfStatement();
2884 while (getLexer().is(AsmToken::Comma)) {
2885 Parser.Lex(); // Eat the comma.
2887 // Parse and remember the operand.
2888 if (parseOperand(Operands, Mnemonic)) {
2889 Parser.EatToEndOfStatement();
2895 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2896 Parser.EatToEndOfStatement();
2897 return TokError("unexpected token in argument list");
2900 Parser.Lex(); // Consume the EndOfStatement
2902 // Some instructions, mostly Thumb, have forms for the same mnemonic that
2903 // do and don't have a cc_out optional-def operand. With some spot-checks
2904 // of the operand list, we can figure out which variant we're trying to
2905 // parse and adjust accordingly before actually matching. Reason number
2906 // #317 the table driven matcher doesn't fit well with the ARM instruction
2908 if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
2909 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2910 Operands.erase(Operands.begin() + 1);
2914 // ARM mode 'blx' need special handling, as the register operand version
2915 // is predicable, but the label operand version is not. So, we can't rely
2916 // on the Mnemonic based checking to correctly figure out when to put
2917 // a CondCode operand in the list. If we're trying to match the label
2918 // version, remove the CondCode operand here.
2919 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
2920 static_cast<ARMOperand*>(Operands[2])->isImm()) {
2921 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2922 Operands.erase(Operands.begin() + 1);
2926 // The vector-compare-to-zero instructions have a literal token "#0" at
2927 // the end that comes to here as an immediate operand. Convert it to a
2928 // token to play nicely with the matcher.
2929 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
2930 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
2931 static_cast<ARMOperand*>(Operands[5])->isImm()) {
2932 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
2933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
2934 if (CE && CE->getValue() == 0) {
2935 Operands.erase(Operands.begin() + 5);
2936 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
2943 // Validate context-sensitive operand constraints.
2944 // FIXME: We would really like to be able to tablegen'erate this.
2946 validateInstruction(MCInst &Inst,
2947 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2948 switch (Inst.getOpcode()) {
2951 case ARM::LDRD_POST:
2953 // Rt2 must be Rt + 1.
2954 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2955 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2957 return Error(Operands[3]->getStartLoc(),
2958 "destination operands must be sequential");
2962 // Rt2 must be Rt + 1.
2963 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2964 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2966 return Error(Operands[3]->getStartLoc(),
2967 "source operands must be sequential");
2971 case ARM::STRD_POST:
2973 // Rt2 must be Rt + 1.
2974 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2975 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2977 return Error(Operands[3]->getStartLoc(),
2978 "source operands must be sequential");
2983 // width must be in range [1, 32-lsb]
2984 unsigned lsb = Inst.getOperand(2).getImm();
2985 unsigned widthm1 = Inst.getOperand(3).getImm();
2986 if (widthm1 >= 32 - lsb)
2987 return Error(Operands[5]->getStartLoc(),
2988 "bitfield width must be in range [1,32-lsb]");
2997 processInstruction(MCInst &Inst,
2998 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2999 switch (Inst.getOpcode()) {
3000 case ARM::LDMIA_UPD:
3001 // If this is a load of a single register via a 'pop', then we should use
3002 // a post-indexed LDR instruction instead, per the ARM ARM.
3003 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3004 Inst.getNumOperands() == 5) {
3006 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3007 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3008 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3009 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3010 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3011 TmpInst.addOperand(MCOperand::CreateImm(4));
3012 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3013 TmpInst.addOperand(Inst.getOperand(3));
3017 case ARM::STMDB_UPD:
3018 // If this is a store of a single register via a 'push', then we should use
3019 // a pre-indexed STR instruction instead, per the ARM ARM.
3020 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3021 Inst.getNumOperands() == 5) {
3023 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3024 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3025 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3026 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3027 TmpInst.addOperand(MCOperand::CreateImm(-4));
3028 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3029 TmpInst.addOperand(Inst.getOperand(3));
3034 // If the immediate is in the range 0-7, we really wanted tADDi3.
3035 if (Inst.getOperand(3).getImm() < 8)
3036 Inst.setOpcode(ARM::tADDi3);
3041 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3042 // the ARMInsts array) instead. Getting that here requires awkward
3043 // API changes, though. Better way?
3045 extern MCInstrDesc ARMInsts[];
3047 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3048 return ARMInsts[Opcode];
3051 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3052 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3053 // suffix depending on whether they're in an IT block or not.
3054 unsigned Opc = Inst.getOpcode();
3055 MCInstrDesc &MCID = getInstDesc(Opc);
3056 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3057 assert(MCID.hasOptionalDef() &&
3058 "optionally flag setting instruction missing optional def operand");
3059 assert(MCID.NumOperands == Inst.getNumOperands() &&
3060 "operand count mismatch!");
3061 // Find the optional-def operand (cc_out).
3064 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3067 // If we're parsing Thumb1, reject it completely.
3068 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3069 return Match_MnemonicFail;
3070 // If we're parsing Thumb2, which form is legal depends on whether we're
3072 // FIXME: We don't yet do IT blocks, so just always consider it to be
3073 // that we aren't in one until we do.
3074 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3075 return Match_RequiresITBlock;
3077 // Some high-register supporting Thumb1 encodings only allow both registers
3078 // to be from r0-r7 when in Thumb2.
3079 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3080 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3081 isARMLowRegister(Inst.getOperand(2).getReg()))
3082 return Match_RequiresThumb2;
3083 // Others only require ARMv6 or later.
3084 else if (Opc == ARM::tMOVr && isThumbOne() &&
3085 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3086 isARMLowRegister(Inst.getOperand(1).getReg()))
3087 return Match_RequiresV6;
3088 return Match_Success;
3092 MatchAndEmitInstruction(SMLoc IDLoc,
3093 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3097 unsigned MatchResult;
3098 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3099 switch (MatchResult) {
3102 // Context sensitive operand constraints aren't handled by the matcher,
3103 // so check them here.
3104 if (validateInstruction(Inst, Operands))
3107 // Some instructions need post-processing to, for example, tweak which
3108 // encoding is selected.
3109 processInstruction(Inst, Operands);
3111 Out.EmitInstruction(Inst);
3113 case Match_MissingFeature:
3114 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3116 case Match_InvalidOperand: {
3117 SMLoc ErrorLoc = IDLoc;
3118 if (ErrorInfo != ~0U) {
3119 if (ErrorInfo >= Operands.size())
3120 return Error(IDLoc, "too few operands for instruction");
3122 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3123 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3126 return Error(ErrorLoc, "invalid operand for instruction");
3128 case Match_MnemonicFail:
3129 return Error(IDLoc, "invalid instruction");
3130 case Match_ConversionFail:
3131 return Error(IDLoc, "unable to convert operands to instruction");
3132 case Match_RequiresITBlock:
3133 return Error(IDLoc, "instruction only valid inside IT block");
3134 case Match_RequiresV6:
3135 return Error(IDLoc, "instruction variant requires ARMv6 or later");
3136 case Match_RequiresThumb2:
3137 return Error(IDLoc, "instruction variant requires Thumb2");
3140 llvm_unreachable("Implement any new match types added!");
3144 /// parseDirective parses the arm specific directives
3145 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
3146 StringRef IDVal = DirectiveID.getIdentifier();
3147 if (IDVal == ".word")
3148 return parseDirectiveWord(4, DirectiveID.getLoc());
3149 else if (IDVal == ".thumb")
3150 return parseDirectiveThumb(DirectiveID.getLoc());
3151 else if (IDVal == ".thumb_func")
3152 return parseDirectiveThumbFunc(DirectiveID.getLoc());
3153 else if (IDVal == ".code")
3154 return parseDirectiveCode(DirectiveID.getLoc());
3155 else if (IDVal == ".syntax")
3156 return parseDirectiveSyntax(DirectiveID.getLoc());
3160 /// parseDirectiveWord
3161 /// ::= .word [ expression (, expression)* ]
3162 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
3163 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3165 const MCExpr *Value;
3166 if (getParser().ParseExpression(Value))
3169 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
3171 if (getLexer().is(AsmToken::EndOfStatement))
3174 // FIXME: Improve diagnostic.
3175 if (getLexer().isNot(AsmToken::Comma))
3176 return Error(L, "unexpected token in directive");
3185 /// parseDirectiveThumb
3187 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
3188 if (getLexer().isNot(AsmToken::EndOfStatement))
3189 return Error(L, "unexpected token in directive");
3192 // TODO: set thumb mode
3193 // TODO: tell the MC streamer the mode
3194 // getParser().getStreamer().Emit???();
3198 /// parseDirectiveThumbFunc
3199 /// ::= .thumbfunc symbol_name
3200 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
3201 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
3202 bool isMachO = MAI.hasSubsectionsViaSymbols();
3205 // Darwin asm has function name after .thumb_func direction
3208 const AsmToken &Tok = Parser.getTok();
3209 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
3210 return Error(L, "unexpected token in .thumb_func directive");
3211 Name = Tok.getString();
3212 Parser.Lex(); // Consume the identifier token.
3215 if (getLexer().isNot(AsmToken::EndOfStatement))
3216 return Error(L, "unexpected token in directive");
3219 // FIXME: assuming function name will be the line following .thumb_func
3221 Name = Parser.getTok().getString();
3224 // Mark symbol as a thumb symbol.
3225 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
3226 getParser().getStreamer().EmitThumbFunc(Func);
3230 /// parseDirectiveSyntax
3231 /// ::= .syntax unified | divided
3232 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
3233 const AsmToken &Tok = Parser.getTok();
3234 if (Tok.isNot(AsmToken::Identifier))
3235 return Error(L, "unexpected token in .syntax directive");
3236 StringRef Mode = Tok.getString();
3237 if (Mode == "unified" || Mode == "UNIFIED")
3239 else if (Mode == "divided" || Mode == "DIVIDED")
3240 return Error(L, "'.syntax divided' arm asssembly not supported");
3242 return Error(L, "unrecognized syntax mode in .syntax directive");
3244 if (getLexer().isNot(AsmToken::EndOfStatement))
3245 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3248 // TODO tell the MC streamer the mode
3249 // getParser().getStreamer().Emit???();
3253 /// parseDirectiveCode
3254 /// ::= .code 16 | 32
3255 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
3256 const AsmToken &Tok = Parser.getTok();
3257 if (Tok.isNot(AsmToken::Integer))
3258 return Error(L, "unexpected token in .code directive");
3259 int64_t Val = Parser.getTok().getIntVal();
3265 return Error(L, "invalid operand to .code directive");
3267 if (getLexer().isNot(AsmToken::EndOfStatement))
3268 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
3274 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3279 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3286 extern "C" void LLVMInitializeARMAsmLexer();
3288 /// Force static initialization.
3289 extern "C" void LLVMInitializeARMAsmParser() {
3290 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
3291 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
3292 LLVMInitializeARMAsmLexer();
3295 #define GET_REGISTER_MATCHER
3296 #define GET_MATCHER_IMPLEMENTATION
3297 #include "ARMGenAsmMatcher.inc"